公开(公告)号：US20250107081A1

公开(公告)日：2025-03-27

申请号：US18472230

申请日：2023-09-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Yuan-Chieh Chiu ,  Kuan-Ting Lu ,  Chiung-Kun Huang

IPC: H10B43/27

Abstract: A memory device includes: an interconnect structure, a staircase structure, a dielectric layer and a stop structure. The interconnect structure is located above a substrate. The staircase structure is located above the interconnect structure. The dielectric layer is located above the interconnect structure and covers the staircase structure. The stop structure is located between the interconnect structure and the staircase structure, and between the interconnect structure and the dielectric layer, and the stop structure has an opening exposing the interconnect structure. The first contact extends through the dielectric layer and the opening, and is connected to the interconnect of the interconnect structure. The middle width of the opening is not equal to the top width of the opening, or the middle width of the opening is not equal to the bottom width of the opening. The memory device may be 3D NAND flash memory with high capacity and high performance.