公开(公告)号：US10770476B1

公开(公告)日：2020-09-08

申请号：US16371579

申请日：2019-04-01

Applicant: MACRONIX International Co., Ltd.

Inventor： Yao-An Chung ,  Yuan-Chieh Chiu

IPC: H01L27/11582 ,  H01L29/792 ,  H01L27/11568 ,  H01L21/28

Abstract: A semiconductor structure for three-dimensional memory device and a manufacturing method thereof are provided. In the manufacturing method, clean plasma is used to clean the impurity doped regions, formed by slit etching, in the surface layer of the substrate to decrease the contact resistance between substrate and conductive plugs formed in the slits. The bottom part of the conductive plugs each has a reduced neck structure and an enlarged bottom structure.

公开(公告)号：US20250107081A1

公开(公告)日：2025-03-27

申请号：US18472230

申请日：2023-09-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Yuan-Chieh Chiu ,  Kuan-Ting Lu ,  Chiung-Kun Huang

IPC: H10B43/27

Abstract: A memory device includes: an interconnect structure, a staircase structure, a dielectric layer and a stop structure. The interconnect structure is located above a substrate. The staircase structure is located above the interconnect structure. The dielectric layer is located above the interconnect structure and covers the staircase structure. The stop structure is located between the interconnect structure and the staircase structure, and between the interconnect structure and the dielectric layer, and the stop structure has an opening exposing the interconnect structure. The first contact extends through the dielectric layer and the opening, and is connected to the interconnect of the interconnect structure. The middle width of the opening is not equal to the top width of the opening, or the middle width of the opening is not equal to the bottom width of the opening. The memory device may be 3D NAND flash memory with high capacity and high performance.

公开(公告)号：US10607848B2

公开(公告)日：2020-03-31

申请号：US15955549

申请日：2018-04-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Yuan-Chieh Chiu ,  Shih-Ping Hong ,  Kuang-Chao Chen ,  Yen-Ju Chen

IPC: H01L21/311 ,  H01L23/485 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3105 ,  H01L23/532 ,  H01L23/31 ,  H01L21/28 ,  H01L33/44 ,  H01L31/18

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

公开(公告)号：US10424593B2

公开(公告)日：2019-09-24

申请号：US15866132

申请日：2018-01-09

Applicant: MACRONIX International Co., Ltd.

Inventor： I-Ting Lin ,  Yuan-Chieh Chiu ,  Hong-Ji Lee

IPC: H01L27/11578 ,  G11C14/00 ,  G11C16/04 ,  H01L21/28 ,  H01L27/1157 ,  G11C16/34 ,  G11C11/56

Abstract: A three-dimensional non-volatile memory and a method of manufacturing the same are provided. The three-dimensional non-volatile memory includes a substrate, a charge storage structure, a stacked structure and a channel layer. The charge storage structure is disposed on the substrate. The stacked structure is disposed at a side of the charge storage structure and includes insulating layers, gates, a buffer layer and a barrier layer. The insulating layers and the gates are alternately stacked. The buffer layer is disposed between each of the gates and the charge storage structure and on the surfaces of the insulating layers. The barrier layer is disposed between each of the gates and the buffer layer. An end of the gate is convex with respect to an end of the barrier layer in a direction away from the channel layer.

公开(公告)号：US11991882B2

公开(公告)日：2024-05-21

申请号：US17528068

申请日：2021-11-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Yao-An Chung ,  Yuan-Chieh Chiu ,  Ting-Feng Liao ,  Kuang-Wen Liu ,  Kuang-Chao Chen

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L23/48 ,  H01L29/51

CPC classification number: H10B43/27 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/481 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518

Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

公开(公告)号：US20220077187A1

公开(公告)日：2022-03-10

申请号：US17528068

申请日：2021-11-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Yao-An Chung ,  Yuan-Chieh Chiu ,  Ting-Feng Liao ,  Kuang-Wen Liu ,  Kuang-Chao Chen

IPC: H01L27/11582 ,  H01L23/48 ,  H01L29/51 ,  H01L21/02 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311

Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

公开(公告)号：US20170053867A1

公开(公告)日：2017-02-23

申请号：US14827971

申请日：2015-08-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Yuan-Chieh Chiu ,  Shih-Ping Hong ,  Yao-An Chung

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/48 ,  H01L23/528

CPC classification number: H01L23/5222 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329

Abstract: Provided is a memory device including a plurality of first conductive line layers, a plurality of support structures, and a charge storage layer. Each of the first conductive line layers extends along a plane defined by a first direction and a second direction. Each of the first conductive line layers includes a plurality of first conductive lines extending along the first direction. The support structures are located between the adjacent first conductive line layers. The charge storage layer covers upper surfaces, lower surfaces, and two side surfaces of the first conductive lines and surfaces of the support structures.

Abstract translation: 提供了包括多个第一导电线层，多个支撑结构和电荷存储层的存储器件。 每个第一导电线层沿着由第一方向和第二方向限定的平面延伸。 每个第一导线层包括沿着第一方向延伸的多个第一导电线。 支撑结构位于相邻的第一导线层之间。 电荷存储层覆盖第一导电线的上表面，下表面和两个侧表面以及支撑结构的表面。

公开(公告)号：US09559049B1

公开(公告)日：2017-01-31

申请号：US14827971

申请日：2015-08-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Yuan-Chieh Chiu ,  Shih-Ping Hong ,  Yao-An Chung

IPC: H01L45/00 ,  H01L43/12 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/48

CPC classification number: H01L23/5222 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329

Abstract: Provided is a memory device including a plurality of first conductive line layers, a plurality of support structures, and a charge storage layer. Each of the first conductive line layers extends along a plane defined by a first direction and a second direction. Each of the first conductive line layers includes a plurality of first conductive lines extending along the first direction. The support structures are located between the adjacent first conductive line layers. The charge storage layer covers upper surfaces, lower surfaces, and two side surfaces of the first conductive lines and surfaces of the support structures.

Abstract translation: 提供了包括多个第一导电线层，多个支撑结构和电荷存储层的存储器件。 每个第一导电线层沿着由第一方向和第二方向限定的平面延伸。 每个第一导线层包括沿着第一方向延伸的多个第一导电线。 支撑结构位于相邻的第一导线层之间。 电荷存储层覆盖第一导电线的上表面，下表面和两个侧表面以及支撑结构的表面。

公开(公告)号：US11211401B2

公开(公告)日：2021-12-28

申请号：US16728394

申请日：2019-12-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Yao-An Chung ,  Yuan-Chieh Chiu ,  Ting-Feng Liao ,  Kuang-Wen Liu ,  Kuang-Chao Chen

IPC: H01L27/115 ,  H01L27/11582 ,  H01L23/48 ,  H01L29/51 ,  H01L21/02 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311

Abstract: A memory device includes a substrate. A first dielectric layer is disposed over the substrate. A plurality of conductive layers and a plurality of dielectric layers are alternately and horizontally disposed on the substrate. A channel column structure is disposed on the substrate and in the conductive layers and the dielectric layers. A side wall of the channel column structure is in contact with the plurality of conductive layers. A second dielectric layer covers the first dielectric layer. A conductive column structure is in the first and second dielectric layers, adjacent to the channel column structure, and in contact with one of the plurality of conductive layers. The conductive column structure includes a liner insulating layer as a shell layer.

公开(公告)号：US20210202518A1

公开(公告)日：2021-07-01

申请号：US16728394

申请日：2019-12-27

Applicant: MACRONIX International Co., Ltd.

Inventor： YAO-AN CHUNG ,  Yuan-Chieh Chiu ,  Ting-Feng Liao ,  Kuang-Wen Liu ,  Kuang-Chao Chen

IPC: H01L27/11582 ,  H01L23/48 ,  H01L29/51 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L21/768

Abstract: A memory device includes a substrate. A first dielectric layer is disposed over the substrate. A plurality of conductive layers and a plurality of dielectric layers are alternately and horizontally disposed on the substrate. A channel column structure is disposed on the substrate and in the conductive layers and the dielectric layers. A side wall of the channel column structure is in contact with the plurality of conductive layers. A second dielectric layer covers the first dielectric layer. A conductive column structure is in the first and second dielectric layers, adjacent to the channel column structure, and in contact with one of the plurality of conductive layers. The conductive column structure includes a liner insulating layer as a shell layer.