公开(公告)号：US20220238549A1

公开(公告)日：2022-07-28

申请号：US17160066

申请日：2021-01-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Chung Yi Lin ,  Chih-Hsiung Lee

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11568

Abstract: Provided are a three-dimensional (3D) memory device and a manufacturing method thereof. The 3D memory device includes a gate stacked structure, a channel layer, a charge storage structure, an electrode layer and a capacitor dielectric layer. The gate stacked structure is disposed on a substrate and includes a plurality of gate layers electrically insulated from each other. The gate stacked structure has at least one channel hole and at least one capacitor trench. The channel layer is disposed on the sidewall of the at least one channel hole. The charge storage structure is disposed between the channel layer and the sidewall of the at least one channel hole. The electrode layer is disposed on the sidewall of the at least one capacitor trench. The capacitor dielectric layer is disposed between the electrode layer and the sidewall of the at least one capacitor trench.

公开(公告)号：US11690223B2

公开(公告)日：2023-06-27

申请号：US17160066

申请日：2021-01-27

Applicant: MACRONIX International Co., Ltd.

Inventor： Chung Yi Lin ,  Chih-Hsiung Lee

IPC: H01L21/00 ,  H10B43/27 ,  H10B43/10 ,  H10B43/30

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/30

Abstract: Provided are a three-dimensional (3D) memory device and a manufacturing method thereof. The 3D memory device includes a gate stacked structure, a channel layer, a charge storage structure, an electrode layer and a capacitor dielectric layer. The gate stacked structure is disposed on a substrate and includes a plurality of gate layers electrically insulated from each other. The gate stacked structure has at least one channel hole and at least one capacitor trench. The channel layer is disposed on the sidewall of the at least one channel hole. The charge storage structure is disposed between the channel layer and the sidewall of the at least one channel hole. The electrode layer is disposed on the sidewall of the at least one capacitor trench. The capacitor dielectric layer is disposed between the electrode layer and the sidewall of the at least one capacitor trench.