公开(公告)号：US20200186401A1

公开(公告)日：2020-06-11

申请号：US16525723

申请日：2019-07-30

Applicant: MARVELL INTERNATIONAL LTD.

Inventor： Krishnan S. Rengarajan ,  Vaibhav A. Ruparelia

IPC: H04L25/03 ,  G06F1/3203 ,  H03M7/42 ,  H03K19/177 ,  H04L27/01

Abstract: A distributed arithmetic feed forward equalizer (DAFFE) and method. The DAFFE includes look-up tables (LUTs) in offset binary format. A DA LUT stores sum of partial products values and an adjustment LUT stores adjustment values. DA LUT addresses are formed from same-position bits from all but the most significant bits (MSBs) of a set of digital words of taps and an adjustment LUT address is formed using the MSBs. Sum of partial products values and an adjustment value are acquired from the DA LUT and the adjustment LUT using the DA LUT addresses and the adjustment LUT address, respectively. Reduced complexity downstream adder(s) (which result in reduced power consumption) compute a total sum of the sum of partial products values and the adjustment value (which compensates for using the offset binary format and dropping of the MSBs when forming the DA LUT addresses) to correctly solve a DA equation.

公开(公告)号：US10721104B2

公开(公告)日：2020-07-21

申请号：US16525723

申请日：2019-07-30

Applicant: MARVELL INTERNATIONAL LTD.

Inventor： Krishnan S. Rengarajan ,  Vaibhav A. Ruparelia

IPC: G06F1/3203 ,  H04L25/03 ,  H04L27/01 ,  H03K19/17728 ,  H03M7/42

Abstract: A distributed arithmetic feed forward equalizer (DAFFE) and method. The DAFFE includes look-up tables (LUTs) in offset binary format. A DA LUT stores sum of partial products values and an adjustment LUT stores adjustment values. DA LUT addresses are formed from same-position bits from all but the most significant bits (MSBs) of a set of digital words of taps and an adjustment LUT address is formed using the MSBs. Sum of partial products values and an adjustment value are acquired from the DA LUT and the adjustment LUT using the DA LUT addresses and the adjustment LUT address, respectively. Reduced complexity downstream adder(s) (which result in reduced power consumption) compute a total sum of the sum of partial products values and the adjustment value (which compensates for using the offset binary format and dropping of the MSBs when forming the DA LUT addresses) to correctly solve a DA equation.

公开(公告)号：US10659017B1

公开(公告)日：2020-05-19

申请号：US16216369

申请日：2018-12-11

Applicant: MARVELL INTERNATIONAL LTD.

Inventor： Krishnan S. Rengarajan ,  Alok Chandra ,  Chethan Ramanna

IPC: H03K3/3562 ,  G01R31/3185 ,  G01R31/317 ,  H03K3/012

Abstract: Disclosed are scan flip-flops (SFFs) that reduce the dynamic power consumption of a system-on-chip (SOC) that incorporates them. Each SFF includes a master latch and a slave latch, each having a driver, a feed-forward path and a feedback path. Each SFF further includes at least one shared clock-gated power supply transistor, which is controlled by either a clock signal or an inverted clock signal to selectively and simultaneously connect a voltage rail to both the driver from one latch and the feedback path of the other latch. The different SFF embodiments have different numbers of shared clock-gated power supply transistors and various other different features designed for optimal power and/or performance. For example, the different SFF embodiments have different types of slave latch drivers; different types of transistors; and/or different types of master latch drivers (e.g., a single-stage, multiple clock phase-dependent driver or a multi-stage, single clock phase-dependent driver).

公开(公告)号：US20200186131A1

公开(公告)日：2020-06-11

申请号：US16216369

申请日：2018-12-11

Applicant: MARVELL INTERNATIONAL LTD.

Inventor： Krishnan S. Rengarajan ,  Alok Chandra ,  Chethan Ramanna

IPC: H03K3/037 ,  H03K3/012 ,  G01R31/317 ,  G01R31/3185

Abstract: Disclosed are scan flip-flops (SFFs) that reduce the dynamic power consumption of a system-on-chip (SOC) that incorporates them. Each SFF includes a master latch and a slave latch, each having a driver, a feed-forward path and a feedback path. Each SFF further includes at least one shared clock-gated power supply transistor, which is controlled by either a clock signal or an inverted clock signal to selectively and simultaneously connect a voltage rail to both the driver from one latch and the feedback path of the other latch. The different SFF embodiments have different numbers of shared clock-gated power supply transistors and various other different features designed for optimal power and/or performance. For example, the different SFF embodiments have different types of slave latch drivers; different types of transistors; and/or different types of master latch drivers (e.g., a single-stage, multiple clock phase-dependent driver or a multi-stage, single clock phase-dependent driver).