公开(公告)号：US6271070B2

公开(公告)日：2001-08-07

申请号：US20656198

申请日：1998-12-08

Applicant: MATSUSHITA ELECTRONICS CORP

Inventor： KOTANI NAOKI ,  SHIMIZU KEIICHIRO

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/8249 ,  H01L21/8238

CPC classification number: H01L21/763 ,  H01L21/76202 ,  H01L21/8249

Abstract: On a main surface of a p-type silicon substrate having a bipolar transistor forming region and a MOS transistor forming region, an epitaxial layer is grown and n-type buried layers are formed. After forming a trench penetrating the buried layer, a buried polysilicon layer is formed in the trench. Then, a threshold control layer, a punch-through stopper layer, a channel stopper layer, an n-type well layer and a p-type well layer of each MOSFET are formed. At this point, since the well layer is formed through high energy ion implantation, the n-type buried layer is suppressed from being enlarged, and hence, time required for forming the trench can be shortened. Thus, a practical method of manufacturing a semiconductor device is provided.

Abstract translation: 在具有双极晶体管形成区域和MOS晶体管形成区域的p型硅衬底的主表面上，生长外延层并形成n型掩埋层。 在形成穿透掩埋层的沟槽之后，在沟槽中形成掩埋多晶硅层。 然后，形成每个MOSFET的阈值控制层，穿通停止层，沟道阻挡层，n型阱层和p型阱层。 此时，由于通过高能离子注入形成了阱层，因此能够抑制n型掩埋层的扩大，能够缩短形成沟槽所需的时间。 因此，提供了制造半导体器件的实用方法。