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公开(公告)号：US6271070B2
公开(公告)日：2001-08-07
申请号：US20656198
申请日：1998-12-08
Applicant: MATSUSHITA ELECTRONICS CORP
Inventor： KOTANI NAOKI , SHIMIZU KEIICHIRO
IPC: H01L21/762 , H01L21/763 , H01L21/8249 , H01L21/8238
CPC classification number: H01L21/763 , H01L21/76202 , H01L21/8249
Abstract: On a main surface of a p-type silicon substrate having a bipolar transistor forming region and a MOS transistor forming region, an epitaxial layer is grown and n-type buried layers are formed. After forming a trench penetrating the buried layer, a buried polysilicon layer is formed in the trench. Then, a threshold control layer, a punch-through stopper layer, a channel stopper layer, an n-type well layer and a p-type well layer of each MOSFET are formed. At this point, since the well layer is formed through high energy ion implantation, the n-type buried layer is suppressed from being enlarged, and hence, time required for forming the trench can be shortened. Thus, a practical method of manufacturing a semiconductor device is provided.
Abstract translation: 在具有双极晶体管形成区域和MOS晶体管形成区域的p型硅衬底的主表面上，生长外延层并形成n型掩埋层。 在形成穿透掩埋层的沟槽之后，在沟槽中形成掩埋多晶硅层。 然后，形成每个MOSFET的阈值控制层，穿通停止层，沟道阻挡层，n型阱层和p型阱层。 此时，由于通过高能离子注入形成了阱层，因此能够抑制n型掩埋层的扩大，能够缩短形成沟槽所需的时间。 因此，提供了制造半导体器件的实用方法。
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公开(公告)号：US3922710A
公开(公告)日：1975-11-25
申请号：US46631974
申请日：1974-05-02
Applicant: MATSUSHITA ELECTRONICS CORP
Inventor： KOIKE SUSUMU
IPC: G11C16/04 , H01L23/29 , H01L29/00 , H01L29/792 , H03K3/26 , H03K3/356 , H01L29/88 , H01L29/34 , H01L29/78 , H01L29/90
CPC classification number: H03K3/356008 , G11C16/0466 , H01L23/291 , H01L24/06 , H01L29/00 , H01L29/792 , H01L2924/12036 , H01L2924/1306 , H03K3/26 , H03K3/356 , Y10S148/114 , H01L2924/00
Abstract: A first thin insulating film capable of being pierced or punched through by carriers such as an SiO2 film 20 A thick is deposited on the surface of a P-type silicon substrate and a second insulating film with a trap level such as an Si3N4 film 500 to 600 A thick is laid on the first insulating film. Upon application of an electric field through a metal electrode mounted on the second insulating film to the combination of the insulating films, electrons captured at the trap level of the second insulating film transfer through the first insulating film to the surface of the substrate thereby forming an inversion layer. When the inversion layer is connected with the two junction regions formed in the surface of the substrate, the reverse current level of the junction region increases semipermanently due to the breakdown voltage of the junction until the inversion layer is cancelled by the application of a reverse electric field. This principle is used to produce a memory device characterized by an exact operation comprising a semiconductor, the first thin insulating film, the second insulating film with a trap level, the second insulating film, the metal electrode and two PN junctions which have different junction breakdown voltages.
Abstract translation: 能够通过诸如SiO 2膜厚度为20A的载体刺穿或穿孔的第一薄薄绝缘膜沉积在P型硅衬底的表面和具有陷阱水平的第二绝缘膜，例如Si 3 N 4膜500至 第一绝缘膜上放置厚度为600。 当通过安装在第二绝缘膜上的金属电极施加电场到绝缘膜的组合时，在第二绝缘膜的陷阱电平处捕获的电子通过第一绝缘膜转移到基板的表面，从而形成 逆温层。 当反型层与形成在衬底的表面中的两个结区连接时，结区的反向电流水平由于结的击穿电压而长时间增加，直到通过施加反向电 领域。 该原理用于制造存储器件，其特征在于精确的操作，其包括半导体，第一薄绝缘膜，具有陷阱级的第二绝缘膜，第二绝缘膜，金属电极和具有不同结断层的两个PN结 电压。
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公开(公告)号：US3910662A
公开(公告)日：1975-10-07
申请号：US40853473
申请日：1973-10-23
Applicant: MATSUSHITA ELECTRONICS CORP
Inventor： FUJIO HINOMARU , FUKUNAGA KAZUNORI , NAKAMURA NAOYUKI
CPC classification number: H01J9/46
Abstract: An apparatus for producing fluorescent lamps comprises an intermittently rotatable turret having a plurality of glass tube supporting arms extending radially from the turret. The apparatus is so arranged that a plurality of glass tubes supported from the supporting arms are simultaneously subjected to working operations such as heating, bending, evacuation, filling, sealing etc. at a plurality of stations in each of which a plurality of glass tubes are subjected to the same working operation to improve the productivity of the apparatus.
Abstract translation: 一种用于生产荧光灯的设备包括间歇旋转的转盘，其具有从转台径向延伸的多个玻璃管支撑臂。 该装置被布置成使得从支撑臂支撑的多个玻璃管同时经受多个工位的加热，弯曲，抽空，填充，密封等工作，其中多个玻璃管是 经受相同的工作操作以提高设备的生产率。
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4.发明授权
公开(公告)号：US3897359A
公开(公告)日：1975-07-29
申请号：US4269270
申请日：1970-06-02
Applicant: MATSUSHITA ELECTRONICS CORP
Inventor： KOBAYASHI YOSHICKIKA , MASUDA MUTSUO , TAKAGAWA MASANORI
CPC classification number: C09K11/7734
Abstract: A phosphor consisting of a solid solution of a complex oxide of alkaline earth metals, aluminum and silicon, which contains oxides of the alkaline earth metals (Ca, Sr and Ba), aluminum and silicon as a host material, which is activated by divalent europium (Eu2 ), shows a bright luminescence spectrum in a wavelength region from near ultraviolet to bluish white, which depends upon the composition of the host material, through an excitation by ultraviolet rays or electron beams. The phosphor is utilized as a blue component for a fluorescent discharge lamp for copying, a flying spot tube, a storage tube or a Braun tube.
Abstract translation: 由碱土金属，铝和硅的复合氧化物的固溶体构成的磷光体，其包含碱土金属（Ca，Sr和Ba）的氧化物，作为主体材料的铝和硅，其被二价铕活化 （Eu 2+），通过紫外线或电子束的激发，显示出从接近紫外线到蓝白色的波长区域中的明亮发光光谱，其取决于主体材料的组成。 荧光体被用作用于复制的荧光放电灯，飞点灯管，储存管或布朗管的蓝色部件。
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公开(公告)号：US3814969A
公开(公告)日：1974-06-04
申请号：US29990972
申请日：1972-10-24
Applicant: MATSUSHITA ELECTRONICS CORP
CPC classification number: C09K11/664 , C09K11/59 , C09K11/74 , C09K11/7738 , C09K11/7776 , H01J61/067
Abstract: A gas discharge tube is provided which comprises a glass tube, a coating of phosphor applied to the inner walls of the glass tube, a pair of electrodes disposed in parallel to each other along the substantial length of the glass tube, and some amounts of mercury and a neon-argon gas mixture or a neon-helium-argon gas mixture.
Abstract translation: 提供一种气体放电管，其包括玻璃管，施加到玻璃管的内壁的荧光体涂层，沿着玻璃管的相当长度彼此平行设置的一对电极，以及一些量的汞 和氖氩气混合物或氖 - 氩气混合物。
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Patent Agency Ranking
公开(公告)号：US3786319A
公开(公告)日：1974-01-15
申请号：US3786319D
申请日：1967-03-20
Applicant: MATSUSHITA ELECTRONICS CORP
Inventor： TOMISABURO O
IPC: H01L23/485 , H01L29/06 , H01L29/78 , H01L19/00
CPC classification number: H01L29/7831 , H01L23/485 , H01L29/0642 , H01L29/0692 , H01L2924/0002 , H01L2924/00
Abstract: A multi-polar insulated gate transistor having two or more isolated electrodes formed on an insulated film, and an island region having a conductivity type different from that of the semiconductor proper and located in the portion of the substrate beneath said film and below the gap between said electrodes, whereby a large current can flow through the element located closer to the drain when the respective elements which may consist of the pair, i.e., each gate and source-island, islandisland or island-drain are under identical voltage conditions.
Abstract translation: 一种多极绝缘栅极晶体管，其具有形成在绝缘膜上的两个或更多个隔离电极，以及岛状区域，其导电类型与半导体本体的导电类型不同，位于所述膜下方的基板部分之下， 所述电极，由此，当可以由一对组成的各个元件即每个栅极和源极岛，岛状岛或岛状漏极处于相同的电压条件下时，大的电流可流过位于更靠近漏极的元件。
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公开(公告)号：US3780330A
公开(公告)日：1973-12-18
申请号：US3780330D
申请日：1972-11-07
Applicant: MATSUSHITA ELECTRONICS CORP
Abstract: Luminous flux and luminous efficiency of a 20 watt fluorescent lamp comprising a ballast specified by the I.E.C. Publication 82 (covering Ballast for fluorescent lamps) is greatly improved by employing an improved tube characterized by: HAVING A NOMINAL TUBE LENGTH OF 590 MM AND AN INNER DIAMETER OF 20 MM TO 25 MM, PROVIDED INSIDE EACH END OF THE TUBE WITH AN ELECTRODE E having a length l of 15 mm to 55 mm inward (from the end face of each cap C as measured as shown in FIG. 2,) and containing mixed rare gas inside the tube, the rare gas having a composition ratio represented by any point within a diagonal region defined by connecting the following points (a) to (e) and (a) with straight lines in the following order, on a trilinear chart for xenon, krypton and argon mixture: (A) Xe: 2%, Kr: 0%, A:98% (b) Xe:15%, Kr: 0%, A:85% (c) Xe:15%, Kr:65%, A:20% (d) Xe:0%, Kr:80%, A:20% (e) Xe:0%, Kr:10%, A:90%, the pressure of the mixed gas being between 1.0 mmHg and 3.5 mmHg at a temperature of 20* C.
Abstract translation: 一种20瓦荧光灯的发光通量和发光效率，包括由I.E.C.规定的镇流器。 出版物82（覆盖荧光灯的镇流器）通过使用改进的管子被大大改进，其特征在于：
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公开(公告)号：US3778660A
公开(公告)日：1973-12-11
申请号：US3778660D
申请日：1971-06-11
Applicant: MATSUSHITA ELECTRONICS CORP
CPC classification number: C09K11/74 , C09K11/0855 , H01J61/44
Abstract: A low pressure mercury vapor fluorescent discharge lamp, having a color rendering value as high as 97 is obtainable by applying on the inner wall of the lamp a layer of a phosphor mixture comprising a basic magnesium arsenate phosphor containing 0.02 0.2 gram-atom of manganese per 6 mols of magnesium oxide, magnesium tungstate, tin-activated strontium magnesium orthophosphate and antimony-and-manganese-activated calcium halophosphate.
Abstract translation: 具有高达97的显色值的低压汞蒸汽荧光放电灯可以通过在灯的内壁上施加包含含有0.02-0.2克原子锰的碱性砷酸镁荧光体的荧光体混合物的层来获得 每6摩尔氧化镁，钨酸镁，锡激活的正磷酸锶镁和锑和锰活化的卤代磷酸钙。
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9.发明授权Ed in the emitter pressure sensitive transistor having a schottky barrier junction form 失效在具有肖特基阻挡结构形式的发射机压力敏感晶体管中的ED
公开(公告)号：US3757176A
公开(公告)日：1973-09-04
申请号：US3757176D
申请日：1971-09-29
Applicant: MATSUSHITA ELECTRONICS CORP
CPC classification number: H04R23/006 , H01L27/0766 , H01L29/00 , Y10S148/15
Abstract: A pressure sensitive semiconductor device which has a schottky barrier junction at an electrode lead-out portion of one region of a p-n-p or n-p-n structure transistor and to which a pressure sensitive junction is formed by providing a pressure applying means to the schottky barrier junction which has a high sensitivity since it amplifies a pressure response signal by the amplifying action of the transistor.
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公开(公告)号：US3742338A
公开(公告)日：1973-06-26
申请号：US3742338D
申请日：1972-03-08
Applicant: MATSUSHITA ELECTRONICS CORP
CPC classification number: G05F3/18
Abstract: A circuit in which the voltage derived from a reference diode or silicon zener diode is fed back through an emitter-follower circuit to the base of a transistor and the constant current flowing through the emitter-collector circuit of the transistor is in turn applied to the reference diode so that such a stabilized output voltage as cannot be attained by the zener diode alone may be obtained.
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