公开(公告)号：US20170188380A1

公开(公告)日：2017-06-29

申请号：US15391779

申请日：2016-12-27

Applicant: MEDIATEK INC.

Inventor： Tsai-Yuan Hsu ,  Chieh-Chao Liu ,  Shih-Chung Yin ,  Kun-Chien Hung ,  Ching-Yu Kuo ,  Hung-Pin Ma

IPC: H04W72/12 ,  H04W74/08

CPC classification number: H04W72/1215 ,  H04W72/0453 ,  H04W74/08 ,  H04W74/0816

Abstract: A time-division mechanism that a source station uses a proprietary frame for notifying switching from a normal bandwidth operation to a narrow bandwidth operation to at least one destination station in a wireless communication system, and uses a protection frame to reserve the service period for the narrow bandwidth operation without the interference from the normal bandwidth operation, wherein the service period of the narrow bandwidth operation is indicated in the protection frame.

公开(公告)号：US10375712B2

公开(公告)日：2019-08-06

申请号：US15391779

申请日：2016-12-27

Applicant: MEDIATEK INC.

Inventor： Tsai-Yuan Hsu ,  Chieh-Chao Liu ,  Shih-Chung Yin ,  Kun-Chien Hung ,  Ching-Yu Kuo ,  Hung-Pin Ma

IPC: H04W72/12 ,  H04W74/08

Abstract: A time-division mechanism that a source station uses a proprietary frame for notifying switching from a normal bandwidth operation to a narrow bandwidth operation to at least one destination station in a wireless communication system, and uses a protection frame to reserve the service period for the narrow bandwidth operation without the interference from the normal bandwidth operation, wherein the service period of the narrow bandwidth operation is indicated in the protection frame.

公开(公告)号：US09094034B2

公开(公告)日：2015-07-28

申请号：US14483137

申请日：2014-09-10

Applicant: MEDIATEK INC.

Inventor： Sheng-Hao Chen ,  Yen-Chuan Huang ,  Min-Hua Wu ,  Chun-Hao Liao ,  Hung-Pin Ma ,  Tzu-Hao Yu ,  Jen-Che Tsai

IPC: H03M1/66 ,  H03M1/06 ,  H03M1/74

CPC classification number: H03M1/0626 ,  H03M1/66 ,  H03M1/74 ,  H03M9/00

Abstract: A digital to analog converting system, which comprises: a first data converting circuit, for receiving a first digital data stream transmitted at a first clock frequency, for converting the first digital data stream to a plurality of second digital data streams transmitted at a second clock frequency, and for outputting the second digital data streams in parallel; a second data converting circuit, for receiving the second digital data streams from the first data converting circuit, and for converting the second digital data streams to a third digital data stream transmitted at a third clock frequency; and a first digital to analog converter, for converting the third digital data stream to a first output analog data stream. The second clock frequency is lower than the first clock frequency and the third clock frequency.

Abstract translation: 一种数模转换系统，包括：第一数据转换电路，用于接收以第一时钟频率发送的第一数字数据流，用于将第一数字数据流转换为在第二时钟发送的多个第二数字数据流 并且用于并行地输出第二数字数据流; 第二数据转换电路，用于从第一数据转换电路接收第二数字数据流，并将第二数字数据流转换成以第三时钟频率发送的第三数字数据流; 以及第一数模转换器，用于将第三数字数据流转换为第一输出模拟数据流。 第二个时钟频率低于第一个时钟频率和第三个时钟频率。

公开(公告)号：US20150123830A1

公开(公告)日：2015-05-07

申请号：US14483137

申请日：2014-09-10

Applicant: MEDIATEK INC.

Inventor： Sheng-Hao Chen ,  Yen-Chuan Huang ,  Min-Hua Wu ,  Chun-Hao Liao ,  Hung-Pin Ma ,  Tzu-Hao Yu ,  Jen-Che Tsai

IPC: H03M1/06 ,  H03M1/74

CPC classification number: H03M1/0626 ,  H03M1/66 ,  H03M1/74 ,  H03M9/00

Abstract: A digital to analog converting system, which comprises: a first data converting circuit, for receiving a first digital data stream transmitted at a first clock frequency, for converting the first digital data stream to a plurality of second digital data streams transmitted at a second clock frequency, and for outputting the second digital data streams in parallel; a second data converting circuit, for receiving the second digital data streams from the first data converting circuit, and for converting the second digital data streams to a third digital data stream transmitted at a third clock frequency; and a first digital to analog converter, for converting the third digital data stream to a first output analog data stream. The second clock frequency is lower than the first clock frequency and the third clock frequency.

Abstract translation: 一种数模转换系统，包括：第一数据转换电路，用于接收以第一时钟频率发送的第一数字数据流，用于将第一数字数据流转换为在第二时钟发送的多个第二数字数据流 并且用于并行地输出第二数字数据流; 第二数据转换电路，用于从第一数据转换电路接收第二数字数据流，并将第二数字数据流转换成以第三时钟频率发送的第三数字数据流; 以及第一数模转换器，用于将第三数字数据流转换为第一输出模拟数据流。 第二个时钟频率低于第一个时钟频率和第三个时钟频率。