公开(公告)号：US20240311542A1

公开(公告)日：2024-09-19

申请号：US18396711

申请日：2023-12-27

Applicant: MEDIATEK INC.

Inventor： Jen-Wei Lee ,  Yi-Ying Liao ,  Te-Wei Chen ,  Kun-Yu Wang ,  Sheng-Tai Tseng ,  Ronald Kuo-Hua Ho ,  Bo-Jiun Hsu ,  Wei-Hsien Lin ,  Chun-Chih Yang ,  Chih-Wei Ko ,  Tai-Lai Tung

IPC: G06F30/392

CPC classification number: G06F30/392

Abstract: A rectilinear-block placement method includes disposing a first sub-block of each flexible block on a layout area of a chip canvas according to a reference position, generating an edge-depth map relative to first sub-blocks of flexible blocks on the layout area, predicting positions of second sub-blocks of the flexible blocks with depth values on the edge-depth map by a machine learning model, and positioning the second sub-blocks on the layout area according to the predicted positions of the second sub-blocks of the flexible blocks.

公开(公告)号：US20250076369A1

公开(公告)日：2025-03-06

申请号：US18637448

申请日：2024-04-16

Applicant: MEDIATEK INC.

Inventor： Ronald Kuo-Hua Ho ,  Kun-Yu Wang ,  Yen-Chang Shih ,  Sung-Te Chen ,  Cheng-Han Wu ,  Yi-Ying Liao ,  Chun-Ming Huang ,  Yen-Feng Lu ,  Ching-Yu Tsai ,  Tai-Lai Tung ,  Kuan-Fu Lin ,  Bo-Kang Lai ,  Yao-Syuan Lee ,  Tsyr-Rou Lin ,  Ming-Chao Tsai ,  Li-Hsuan Chiu

IPC: G01R31/28 ,  G06N3/08 ,  H03K3/01

Abstract: A minimum IC operating voltage searching method includes acquiring a corner type of an IC, acquiring ring oscillator data of the IC, generating a first prediction voltage according to the corner type and the ring oscillator data by using a training model, generating a second prediction voltage according to the ring oscillator data by using a non-linear regression approach under an N-ordered polynomial, and generating a predicted minimum IC operating voltage according to the first prediction voltage and the second prediction voltage. N is a positive integer.

公开(公告)号：US20230376653A1

公开(公告)日：2023-11-23

申请号：US18315904

申请日：2023-05-11

Applicant: MediaTek Inc.

Inventor： Hsin-Chuan Kuo ,  Chia-Wei Chen ,  Yu-Hsiu Lin ,  Kun-Yu Wang ,  Sheng-Tai Tseng ,  Chun-Ku Ting ,  Fang-Ming Yang ,  Yu-Hsien Ku ,  Jen-Wei Lee ,  Ronald Kuo-Hua Ho ,  Chun-Chieh Wang ,  Yi-Ying Liao ,  Tai-Lai Tung ,  Ming-Fang Tsai ,  Chun-Chih Yang ,  Chih-Wei Ko ,  Kun-Chin Huang

IPC: G06F30/27 ,  G06F30/392

CPC classification number: G06F30/27 ,  G06F30/392

Abstract: A neural network is used to place macros on a chip canvas in an integrated circuit (IC) design. The macros are first clustered into multiple macro clusters. Then the neural network generates a probability distribution over locations on a grid and aspect ratios of a macro cluster. The grid represents the chip canvas and is formed by rows and columns of grid cells. The macro cluster is described by at least an area size, aspect ratios, and wire connections. Action masks are generated for respective ones of the aspect ratios to block out a subset of unoccupied grid cells based on design rules that optimize macro placement. Then, by applying the action masks on the probability distribution, a masked probability distribution is generated. Based on the masked probability distribution, a location on the grid is selected for placing the macro cluster with a chosen aspect ratio.