公开(公告)号：US11640184B2

公开(公告)日：2023-05-02

申请号：US16918601

申请日：2020-07-01

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Tseng ,  Mohammed Fathey Abdelfattah Hassan ,  Li-Shin Lai ,  Tzu-Yu Yeh ,  Ming-Da Tsai ,  Bernard Mark Tenbroek

IPC: G06F1/12 ,  G06F1/10 ,  H03K3/037

Abstract: Aspects of the disclosure provide methods and apparatuses for generating an internal reset signal that is synchronous to a clock signal. In some embodiments, an apparatus includes a clock switch circuit and a plurality of serially coupled D flip-flops (DFFs). The clock switch circuit receiving the clock signal can output the clock signal in an on state and block the clock signal in an off state. The plurality of serially coupled DFFs are coupled to the clock switch circuit and driven by the clock signal. If an external reset signal is enabled, the plurality of serially coupled DFFs can enable the internal reset signal. If the external reset signal is disabled, after a predefined number of clock signal cycles, the plurality of serially coupled DFFs can disable the internal reset signal.