利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

5 条记录 (耗时 0.013 秒)

    TRANSMITTER SUPPORTING TWO MODES
    2.
    发明申请
    TRANSMITTER SUPPORTING TWO MODES 有权
    发射机支持两种模式

    公开(公告)号：US20140086360A1

    公开(公告)日：2014-03-27

    申请号：US14037329

    申请日：2013-09-25

    申请人： MEDIATEK INC.

    发明人： Hsiang-Hui Chang ,  Li-Shin Lai ,  Chih-Jung Chen ,  Chih-Hao Sun

    IPC分类号： H04B1/04

    CPC分类号： H04B1/0475 ,  H04B1/0483 ,  H04L27/04

    摘要： A transmitter includes a first channel and a second channel. The first channel includes a first mixer, and is used for processing a first input signal to generate a first output signal; the second channel includes a second mixer, where the second channel does not receive any input signal. When the transmitter is operated under a first mode, both the first mixer and the second mixer receive oscillation signals.

    摘要翻译： 发射机包括第一信道和第二信道。 第一通道包括第一混频器，用于处理第一输入信号以产生第一输出信号; 第二通道包括第二混频器，其中第二通道不接收任何输入信号。 当发射机在第一模式下操作时，第一混频器和第二混频器都接收振荡信号。

    Phase synchronized LO generation
    3.
    发明授权
    Phase synchronized LO generation 有权

    公开(公告)号：US11640184B2

    公开(公告)日：2023-05-02

    申请号：US16918601

    申请日：2020-07-01

    申请人： MEDIATEK INC.

    发明人： Chien-Wei Tseng ,  Mohammed Fathey Abdelfattah Hassan ,  Li-Shin Lai ,  Tzu-Yu Yeh ,  Ming-Da Tsai ,  Bernard Mark Tenbroek

    IPC分类号： G06F1/12 ,  G06F1/10 ,  H03K3/037

    摘要： Aspects of the disclosure provide methods and apparatuses for generating an internal reset signal that is synchronous to a clock signal. In some embodiments, an apparatus includes a clock switch circuit and a plurality of serially coupled D flip-flops (DFFs). The clock switch circuit receiving the clock signal can output the clock signal in an on state and block the clock signal in an off state. The plurality of serially coupled DFFs are coupled to the clock switch circuit and driven by the clock signal. If an external reset signal is enabled, the plurality of serially coupled DFFs can enable the internal reset signal. If the external reset signal is disabled, after a predefined number of clock signal cycles, the plurality of serially coupled DFFs can disable the internal reset signal.

    Transmitter supporting two modes
    4.
    发明授权
    Transmitter supporting two modes 有权
    变送器支持两种模式

    公开(公告)号：US09172408B2

    公开(公告)日：2015-10-27

    申请号：US14037329

    申请日：2013-09-25

    申请人： MEDIATEK INC.

    发明人： Hsiang-Hui Chang ,  Li-Shin Lai ,  Chih-Jung Chen ,  Chih-Hao Sun

    IPC分类号： H04B1/04 ,  H04L27/04

    CPC分类号： H04B1/0475 ,  H04B1/0483 ,  H04L27/04

    摘要： A transmitter includes a first channel and a second channel. The first channel includes a first mixer, and is used for processing a first input signal to generate a first output signal; the second channel includes a second mixer, where the second channel does not receive any input signal. When the transmitter is operated under a first mode, both the first mixer and the second mixer receive oscillation signals.

    摘要翻译： 发射机包括第一信道和第二信道。 第一通道包括第一混频器，用于处理第一输入信号以产生第一输出信号; 第二通道包括第二混频器，其中第二通道不接收任何输入信号。 当发射机在第一模式下操作时，第一混频器和第二混频器都接收振荡信号。