Processor with conditional-fence commands excluding designated memory regions

    公开(公告)号:US11580036B1

    公开(公告)日:2023-02-14

    申请号:US17385962

    申请日:2021-07-27

    Abstract: An apparatus includes a processor, configured to designate a memory region in a memory, and to issue (i) memory-access commands for accessing the memory and (ii) a conditional-fence command associated with the designated memory region. Memory-Access Control Circuitry (MACC) is configured, in response to identifying the conditional-fence command, to allow execution of the memory-access commands that access addresses within the designated memory region, and to defer the execution of the memory-access commands that access addresses outside the designated memory region, until completion of all the memory-access commands that were issued before the conditional-fence command.

    Processor with conditional-fence commands excluding designated memory regions

    公开(公告)号:US20230036954A1

    公开(公告)日:2023-02-02

    申请号:US17385962

    申请日:2021-07-27

    Abstract: An apparatus includes a processor, configured to designate a memory region in a memory, and to issue (i) memory-access commands for accessing the memory and (ii) a conditional-fence command associated with the designated memory region. Memory-Access Control Circuitry (MACC) is configured, in response to identifying the conditional-fence command, to allow execution of the memory-access commands that access addresses within the designated memory region, and to defer the execution of the memory-access commands that access addresses outside the designated memory region, until completion of all the memory-access commands that were issued before the conditional-fence command.

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