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    Processor with conditional-fence commands excluding designated memory regions
    1.
    发明申请
    Processor with conditional-fence commands excluding designated memory regions 有权

    公开(公告)号：US20230036954A1

    公开(公告)日：2023-02-02

    申请号：US17385962

    申请日：2021-07-27

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Ilan Pardo ,  Shahaf Shuler ,  George Elias ,  Nizan Atias ,  Adi Maymon

    IPC: G06F12/14 ,  G06F12/02 ,  G06F9/30

    Abstract: An apparatus includes a processor, configured to designate a memory region in a memory, and to issue (i) memory-access commands for accessing the memory and (ii) a conditional-fence command associated with the designated memory region. Memory-Access Control Circuitry (MACC) is configured, in response to identifying the conditional-fence command, to allow execution of the memory-access commands that access addresses within the designated memory region, and to defer the execution of the memory-access commands that access addresses outside the designated memory region, until completion of all the memory-access commands that were issued before the conditional-fence command.

    Payload cache
    2.
    发明申请
    Payload cache 有权

    公开(公告)号：US20210400124A1

    公开(公告)日：2021-12-23

    申请号：US16908776

    申请日：2020-06-23

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Ilan Pardo ,  Mark B. Rosenbluth ,  Idan Burstein ,  Rui Xu ,  Oded Lempel ,  Tsofia Eshel

    IPC: H04L29/06 ,  G06F12/0875 ,  G06F13/40 ,  H04L29/08 ,  H04L12/879

    Abstract: In one embodiment, a computer system includes a payload sub-system including interfaces to connect with respective devices, transfer data with the respective devices, and receive write transactions from the respective devices, a classifier to classify the received write transactions into payload data and control data, and a payload cache to store the classified payload data, and a processing unit (PU) sub-system including a local PU cache to store the classified control data, wherein the payload cache and the local PU cache are different physical caches in respective different physical locations in the computer system, and processing core circuitry configured to execute software program instructions to perform control and packet processing responsively to the control data stored in the local PU cache.

    Processor with conditional-fence commands excluding designated memory regions
    6.
    发明授权
    Processor with conditional-fence commands excluding designated memory regions 有权

    公开(公告)号：US11580036B1

    公开(公告)日：2023-02-14

    申请号：US17385962

    申请日：2021-07-27

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Ilan Pardo ,  Shahaf Shuler ,  George Elias ,  Nizan Atias ,  Adi Maymon

    IPC: G06F12/14 ,  G06F9/30 ,  G06F12/02

    Abstract: An apparatus includes a processor, configured to designate a memory region in a memory, and to issue (i) memory-access commands for accessing the memory and (ii) a conditional-fence command associated with the designated memory region. Memory-Access Control Circuitry (MACC) is configured, in response to identifying the conditional-fence command, to allow execution of the memory-access commands that access addresses within the designated memory region, and to defer the execution of the memory-access commands that access addresses outside the designated memory region, until completion of all the memory-access commands that were issued before the conditional-fence command.

    Expandable queue
    7.
    发明授权
    Expandable queue 有权

    公开(公告)号：US11558309B1

    公开(公告)日：2023-01-17

    申请号：US17369992

    申请日：2021-07-08

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Ilan Pardo

    IPC: H04L47/625 ,  H04L49/90 ,  H04L49/9005 ,  H04L47/62

    Abstract: A network device includes packet processing circuitry and queue management circuitry. The packet processing circuitry is configured to transmit and receive packets to and from a network. The queue management circuitry is configured to store, in a memory, a queue for queuing data relating to processing of the packets, the queue including a primary buffer and an overflow buffer, to choose between a normal mode and an overflow mode based on a defined condition, to queue the data only in the primary buffer when operating in the normal mode, and, when operating in the overflow mode, to queue the data in a concatenation of the primary buffer and the overflow buffer.

    Cache stashing system
    10.
    发明申请
    Cache stashing system 有权

    公开(公告)号：US20210397560A1

    公开(公告)日：2021-12-23

    申请号：US16907347

    申请日：2020-06-22

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Ilan Pardo ,  Hillel Chapman ,  Mark B. Rosenbluth

    IPC: G06F12/0891 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/54 ,  H04L29/08 ,  H04L29/06

    Abstract: In one embodiment, a computer server system includes a memory to store data across memory locations, multiple processing cores including respective local caches in which to cache cache-lines read from the memory, an interconnect to manage read and write operations of the memory and local caches, maintain local cache location data of the cached cache-lines according to respective ones of the memory locations from which the cached cache-lines were read from the memory, receive a write request for a data element to be written to one of the memory locations, find a local cache location in which to write the data element responsively to the local cache location data and the memory location of the write request, and send an update request to a first processing core to update a respective first local cache with the data element responsively to the found local cache location.

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