公开(公告)号：US20250158739A1

公开(公告)日：2025-05-15

申请号：US19026299

申请日：2025-01-16

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Asaf Horev ,  Ran Ravid ,  Guy Lederman ,  Roman Meltser

IPC: H04L1/00

Abstract: A communication system is described, among other things. An illustrative system is disclosed to include one or more decoding circuits to perform forward error correction for a received data block in a physical layer and one or more cyclic redundancy check circuits to perform a cyclic redundancy check based on a first output of the decoding circuits and a cyclic redundancy check code generated in the physical layer based on the received data block. In response to one or more of a second output of the decoding circuits and an output of the cyclic redundancy check circuits, a retransmission request of the data block is initiated.

公开(公告)号：US20240333423A1

公开(公告)日：2024-10-03

申请号：US18192239

申请日：2023-03-29

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Asaf Horev ,  Ran Ravid ,  Guy Lederman ,  Roman Meltser

IPC: H04L1/00

CPC classification number: H04L1/0057 ,  H04L1/0041

Abstract: A communication system is described, among other things. An illustrative system is disclosed to include one or more decoding circuits to perform forward error correction for a received data block in a physical layer and one or more cyclic redundancy check circuits to perform a cyclic redundancy check based on a first output of the decoding circuits and a cyclic redundancy check code generated in the physical layer based on the received data block. In response to one or more of a second output of the decoding circuits and an output of the cyclic redundancy check circuits, a retransmission request of the data block is initiated.

公开(公告)号：US12244416B2

公开(公告)日：2025-03-04

申请号：US18192239

申请日：2023-03-29

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Asaf Horev ,  Ran Ravid ,  Guy Lederman ,  Roman Meltser

IPC: H03M13/00 ,  H04L1/00

Abstract: A communication system is described, among other things. An illustrative system is disclosed to include one or more decoding circuits to perform forward error correction for a received data block in a physical layer and one or more cyclic redundancy check circuits to perform a cyclic redundancy check based on a first output of the decoding circuits and a cyclic redundancy check code generated in the physical layer based on the received data block. In response to one or more of a second output of the decoding circuits and an output of the cyclic redundancy check circuits, a retransmission request of the data block is initiated.