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    Time synchronization based on network traffic patterns
    1.
    发明授权
    Time synchronization based on network traffic patterns 有权

    公开(公告)号：US11606157B1

    公开(公告)日：2023-03-14

    申请号：US17520674

    申请日：2021-11-07

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Wojciech Wasko ,  Dotan David Levi ,  Guy Lederman

    IPC: H04J3/06 ,  H04L43/06 ,  H04L43/065 ,  H04L43/067

    Abstract: A network node includes a port and circuitry. The port is configured for communicating over a packet network. The circuitry is configured to receive, via the port, a sequence of packets from a peer network node, the sequence of packets including (i) a time-protocol packet and (ii) a transmit-side (TX) time-stamp indicative of a time at which the time-protocol packet was transmitted from the peer network node, to assess a receive-side (RX) traffic pattern over one or more of the received packets in the sequence that precede reception of the time-protocol packet, and to calculate an accuracy measure for the TX time-stamp, based on the assessed RX traffic pattern.

    SYSTEMS AND METHODS OF INITIATING RETRANSMISSION REQUESTS
    3.
    发明公开
    SYSTEMS AND METHODS OF INITIATING RETRANSMISSION REQUESTS 审中-公开

    公开(公告)号：US20240333423A1

    公开(公告)日：2024-10-03

    申请号：US18192239

    申请日：2023-03-29

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Asaf Horev ,  Ran Ravid ,  Guy Lederman ,  Roman Meltser

    IPC: H04L1/00

    CPC classification number: H04L1/0057 ,  H04L1/0041

    Abstract: A communication system is described, among other things. An illustrative system is disclosed to include one or more decoding circuits to perform forward error correction for a received data block in a physical layer and one or more cyclic redundancy check circuits to perform a cyclic redundancy check based on a first output of the decoding circuits and a cyclic redundancy check code generated in the physical layer based on the received data block. In response to one or more of a second output of the decoding circuits and an output of the cyclic redundancy check circuits, a retransmission request of the data block is initiated.

    Link efficient power state management for multi-segment switched fabrics
    4.
    发明公开
    Link efficient power state management for multi-segment switched fabrics 审中-公开

    公开(公告)号：US20240039689A1

    公开(公告)日：2024-02-01

    申请号：US17994326

    申请日：2022-11-27

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Roman Meltser ,  Guy Lederman ,  Ran Ravid ,  Zvi Rechtman ,  Lavi Koch

    IPC: H04L7/02

    CPC classification number: H04L7/02

    Abstract: In one embodiment, a retimer device includes a receiver to receive data from a first device via a data link, retimer circuitry to recover a clock phase from the received data, and prepare a new copy of the received data sampled by a clean clock based on the recovered clock phase, a transmitter to transmit the new copy to a second device via the data link, wherein the receiver is configured to receive an in-band standby signal from the first device having a given pattern in a physical layer of the signal, activate a power saving mode of the retimer device responsively to the standby signal having the given pattern in the physical layer of the standby signal, receive an in-band wakeup signal from the first device, and initiate an exit from the power saving mode to power up the retimer device responsively to the wakeup signal.

    Systems and methods of initiating retransmission requests
    6.
    发明授权
    Systems and methods of initiating retransmission requests 有权

    公开(公告)号：US12244416B2

    公开(公告)日：2025-03-04

    申请号：US18192239

    申请日：2023-03-29

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Asaf Horev ,  Ran Ravid ,  Guy Lederman ,  Roman Meltser

    IPC: H03M13/00 ,  H04L1/00

    Abstract: A communication system is described, among other things. An illustrative system is disclosed to include one or more decoding circuits to perform forward error correction for a received data block in a physical layer and one or more cyclic redundancy check circuits to perform a cyclic redundancy check based on a first output of the decoding circuits and a cyclic redundancy check code generated in the physical layer based on the received data block. In response to one or more of a second output of the decoding circuits and an output of the cyclic redundancy check circuits, a retransmission request of the data block is initiated.

    Packet scheduling system with desired physical transmission time for packets
    7.
    发明申请
    Packet scheduling system with desired physical transmission time for packets 有权

    公开(公告)号：US20210409137A1

    公开(公告)日：2021-12-30

    申请号：US16910193

    申请日：2020-06-24

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Liron Mula ,  Dotan David Levi ,  Ran Ravid ,  Guy Lederman

    IPC: H04J3/06 ,  H04L29/06 ,  H04L12/46 ,  H04L12/26

    Abstract: In certain exemplary embodiments, a switching device is provided, including an input interface configured to communicate with a packet source, an output interface configured to communicate with a packet destination, and packet processing circuitry. The packet processing circuitry is configured to receive a plurality of packets from the packet source via the input interface, each of the plurality of packets being associated with a packet descriptor, at least one of the packet descriptors being a transmission time packet descriptor including a desired physical transmission time for the packet associated with the transmission time packet descriptor, to receive an indication of a clock time, and for each packet associated with a transmission time packet descriptor, to physically transmit the packet associated with the transmission time packet descriptor, via the output interface, at a clock time corresponding to the desired physical transmission time. Related apparatus an methods are also provided.

    Receive-side timestamp accuracy
    8.
    发明申请
    Receive-side timestamp accuracy 有权

    公开(公告)号：US20210392065A1

    公开(公告)日：2021-12-16

    申请号：US16900931

    申请日：2020-06-14

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Ran Sela ,  Liron Mula ,  Ran Ravid ,  Guy Lederman ,  Dotan David Levi

    IPC: H04L12/26 ,  H04J3/06

    Abstract: In one embodiment, a network device, includes a network interface port configured to receive data symbols from a network node over a packet data network, at least some of the symbols being included in data packets, and controller circuitry including physical layer (PHY) circuitry, which includes receive PHY pipeline circuitry configured to process the received data symbols, and a counter configured to maintain a counter value indicative of a number of the data symbols in the receive PHY pipeline circuitry.

    PHYSICAL LAYER SYNCHRONIZATION
    9.
    发明申请
    PHYSICAL LAYER SYNCHRONIZATION 有权

    公开(公告)号：US20240373379A1

    公开(公告)日：2024-11-07

    申请号：US18225525

    申请日：2023-07-24

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Liron Mula ,  Ariel Almog ,  Bar Shapira ,  Guy Lederman

    IPC: H04W56/00

    Abstract: A system including an interconnect device coupled with one or more devices where the first device of the one or more devices is to transmit a control block for synchronization via a physical layer of a link coupled to the high-speed interconnect device, the control block comprising a header portion of bits corresponding to a header indicating the block is a control block and a data portion of bits indicating the control block is associated with time synchronization information. The interconnect device is to receive data, parse the data, determine the data is associated with the control block, determine a delay associated with the physical layer transmitting the control block and transmitting a signal responsive to receiving the control block and determining the delay.

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