公开(公告)号：US12068968B2

公开(公告)日：2024-08-20

申请号：US17588295

申请日：2022-01-30

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gal Yefet ,  Saar Tarnopolsky ,  Avi Urman ,  Dotan David Levi ,  Elena Agostini

IPC: H04L47/2441 ,  H04L47/6295 ,  H04L69/22

CPC classification number: H04L47/2441 ,  H04L69/22

Abstract: In one embodiments, data communication system include a communication apparatus, which is configured to receive data from different user equipment devices a schedule of time periods, and packetize the data from respective ones of the user equipment devices for respective ones of the time periods into packets, a memory including a plurality of buffers, and a network interface controller configured to receive the packets from the communication apparatus, and scatter respective portions of the data belonging to respective groups of successive ones of the time periods to the buffers, responsively to a static set of steering rules, and timing information of respective ones of the packets, and wherein each respective portion of the data is scattered to the buffers a same scatter pattern.

公开(公告)号：US20240364642A1

公开(公告)日：2024-10-31

申请号：US18512961

申请日：2023-11-17

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Elena Agostini ,  Brent David Schartung ,  Wei Zhang

IPC: H04L49/90 ,  H04L69/22

CPC classification number: H04L49/90 ,  H04L69/22

Abstract: A system for transmitting data is described, among other things. An illustrative system is disclosed to include one or more circuits to perform receiving a first packet, determining a header of the first packet includes a SYN, FIN, or RST flag, in response, delivering the first packet to a CPU, receiving a second packet, determining a header of the second packet does not include a SYN, FIN, or RST flag, and, in response, deliver the second packet to a GPU.

公开(公告)号：US20240078185A1

公开(公告)日：2024-03-07

申请号：US17947857

申请日：2022-09-19

Applicant: Mellanox Technologies, Ltd.

Inventor： Elena Agostini

IPC: G06F12/0884

CPC classification number: G06F12/0884 ,  G06F2212/163

Abstract: Apparatuses, systems, and techniques of using parallel processor(s), such as one or more graphics processing units, to process packets (e.g., in real time). In at least one embodiment, a processor (e.g., a parallel processing unit, a central processing unit, and/or the like) detects when packet data has been stored in a memory accessible by the parallel processing unit. Then, the parallel processing unit may process the packet data to produce output data.

公开(公告)号：US20230291693A1

公开(公告)日：2023-09-14

申请号：US17588295

申请日：2022-01-30

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gal Yefet ,  Saar Tarnopolsky ,  Avi Urman ,  Dotan David Levi ,  Elena Agostini

IPC: H04L47/2441 ,  H04L69/22

CPC classification number: H04L47/2441 ,  H04L69/22

Abstract: In one embodiments, data communication system include a communication apparatus, which is configured to receive data from different user equipment devices a schedule of time periods, and packetize the data from respective ones of the user equipment devices for respective ones of the time periods into packets, a memory including a plurality of buffers, and a network interface controller configured to receive the packets from the communication apparatus, and scatter respective portions of the data belonging to respective groups of successive ones of the time periods to the buffers, responsively to a static set of steering rules, and timing information of respective ones of the packets, and wherein each respective portion of the data is scattered to the buffers a same scatter pattern.