公开(公告)号：US12068968B2

公开(公告)日：2024-08-20

申请号：US17588295

申请日：2022-01-30

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gal Yefet ,  Saar Tarnopolsky ,  Avi Urman ,  Dotan David Levi ,  Elena Agostini

IPC: H04L47/2441 ,  H04L47/6295 ,  H04L69/22

CPC classification number: H04L47/2441 ,  H04L69/22

Abstract: In one embodiments, data communication system include a communication apparatus, which is configured to receive data from different user equipment devices a schedule of time periods, and packetize the data from respective ones of the user equipment devices for respective ones of the time periods into packets, a memory including a plurality of buffers, and a network interface controller configured to receive the packets from the communication apparatus, and scatter respective portions of the data belonging to respective groups of successive ones of the time periods to the buffers, responsively to a static set of steering rules, and timing information of respective ones of the packets, and wherein each respective portion of the data is scattered to the buffers a same scatter pattern.

公开(公告)号：US20240146664A1

公开(公告)日：2024-05-02

申请号：US17979018

申请日：2022-11-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gal Yefet ,  Daniel Marcovitch ,  Roee Moyal ,  Gil Bloch ,  Ariel Shahar ,  Yossef Itigin

IPC: H04L47/625 ,  H04L47/62 ,  H04L47/6275

CPC classification number: H04L47/6255 ,  H04L47/6225 ,  H04L47/6275

Abstract: In one embodiment, a system includes a memory to store a work queue including work queue entry slots, a processing device to write work queue entries to the work queue in a consecutive and cyclic manner, and a network device including a network interface to share packet over a network, and packet processing circuitry to read the work queue entries from the work queue in a consecutive and cyclic manner, the work queue entries indicating work to be performed associated with the packets, dequeue respective ones of the work queue entries read from the work queue responsively to reading the respective work queue entries from the work queue, add the work queue entries to an execution database used to track execution of the work queue entries, and execute the work queue entries in the execution database.

公开(公告)号：US11792139B2

公开(公告)日：2023-10-17

申请号：US17582047

申请日：2022-01-24

Applicant: Mellanox Technologies, Ltd.

Inventor： Boris Pismenny ,  Ben Ben Ishay ,  Gal Yefet ,  Gil Kremer ,  Avi Urman ,  Yorai Itzhak Zack ,  Khalid Manaa ,  Liran Liss

IPC: H04L69/22 ,  H04L49/90 ,  H04L49/9057

CPC classification number: H04L49/9057 ,  H04L49/9042 ,  H04L69/22

Abstract: A peripheral device coupled to a host includes a network interface, a packet processor, and a Data Processing Unit (DPU). The packet processor receives from a communication network, via the network interface, packets that originated from a source in an original order and received at the peripheral device in as order different from the original order. The packet processor splits the received packets into headers and payloads, sends the payloads for storage in a host memory and sends the headers without the payloads for storage in a DPU memory, and based on the headers produces a hint indicative of processing to be applied to the headers, by the DPU, for identifying the original order. Based on the hint, the DPU identifies the original order of the packets by applying the processing indicated by the hint to respective headers in the DPU memory, and notifies the host of the original order.

公开(公告)号：US20230141761A1

公开(公告)日：2023-05-11

申请号：US18090538

申请日：2022-12-29

Applicant: Mellanox Technologies, Ltd.

Inventor： Or Gerlitz ,  Noam Bloch ,  Gal Yefet

IPC: H04L67/104 ,  H04L43/062 ,  H04L43/0894 ,  H04L67/00 ,  H04L67/01

CPC classification number: H04L67/1044 ,  H04L43/062 ,  H04L43/0894 ,  H04L67/01 ,  H04L67/34

Abstract: A network device includes a network interface, a host interface, and processing circuitry. The network interface is configured to connect to a communication network. The host interface is configured to connect to a host comprising a host processor running a client process. The processing circuitry is configured to receive packets belonging to a message having a message length, the message originating from a peer process, to identify, in at least some of the received packets, application-level information specifying the message length, to determine, based on the identified message length, that the packets of the message already received comprise only a portion of the message, and in response to determining that the client process benefits from receiving less than the entire message, to initiate reporting the packets of the message already received to the client process.

公开(公告)号：US20240012762A1

公开(公告)日：2024-01-11

申请号：US17887458

申请日：2022-08-14

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gal Yefet ,  Yamin Friedman ,  Daniil Provotorov ,  Ariel Shahar ,  Natan Oppenheimer ,  Ran Avraham Koren ,  Av Urman

IPC: G06F12/0891

CPC classification number: G06F12/0891 ,  G06F2212/60

Abstract: An apparatus for cache management includes an interface and a processor. The interface is for communicating with a cache memory configured to store data items. The cache controller is configured to obtain a classification of the data items into a plurality of groups, to obtain respective target capacities for at least some of the groups, each target capacity defining a respective required size of a portion of the cache memory that is permitted to be occupied by the data items belonging to the group, and to cache new data items in the cache memory, or evict cached data items from the cache memory, in accordance with a policy that complies with the target capacities specified for the groups.

公开(公告)号：US20230239257A1

公开(公告)日：2023-07-27

申请号：US17582047

申请日：2022-01-24

Applicant: Mellanox Technologies, Ltd.

Inventor： Boris Pismenny ,  Ben Ben Ishay ,  Gal Yefet ,  Gil Kremer ,  Avi Urman ,  Yorai Itzhak Zack ,  Khalid Manaa ,  Liran Liss

IPC: H04L49/9057 ,  H04L69/22 ,  H04L49/90

CPC classification number: H04L49/9057 ,  H04L69/22 ,  H04L49/9042

Abstract: A peripheral device coupled to a host includes a network interface, a packet processor, and a Data Processing Unit (DPU). The packet processor receives from a communication network, via the network interface, packets that originated from a source in an original order and received at the peripheral device in as order different from the original order. The packet processor splits the received packets into headers and payloads, sends the payloads for storage in a host memory and sends the headers without the payloads for storage in a DPU memory, and based on the headers produces a hint indicative of processing to be applied to the headers, by the DPU, for identifying the original order. Based on the hint, the DPU identifies the original order of the packets by applying the processing indicated by the hint to respective headers in the DPU memory, and notifies the host of the original order.

公开(公告)号：US20230110316A1

公开(公告)日：2023-04-13

申请号：US17499580

申请日：2021-10-12

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Ilan Pardo ,  Benjamin Fuhrer ,  Galina Ryvchin ,  Gal Yefet

IPC: G06F9/30 ,  G06F17/16 ,  G06F7/544

Abstract: Apparatuses, systems, and techniques to improve processing efficiency. In at least one embodiment, a processing unit includes circuitry that reads a vector from memory and multiplies the vector with a scalar value extracted from a scalar field of a vector register. The scalar field may be specified by an immediate field value that is also used to identify an offset used to define a pointer that points to a location in the memory from which to read the vector.

公开(公告)号：US20220217101A1

公开(公告)日：2022-07-07

申请号：US17142366

申请日：2021-01-06

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Gal Yefet ,  Daniel Marcovitch ,  Roee Moyal ,  Ariel Shahar ,  Gil Bloch ,  Lior Narkis

IPC: H04L12/879 ,  H04L12/861 ,  H04L12/937 ,  H04L12/24

Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface connects to a communication network for communicating with remote targets. The host interface connects to a host that accesses a Multi-Channel Send Queue (MCSQ) storing Work Requests (WRs) originating from client processes running on the host. The processing circuitry is configured to retrieve WRs from the MCSQ and distribute the WRs among multiple Send Queues (SQs) accessible by the processing circuitry.

公开(公告)号：US20210297151A1

公开(公告)日：2021-09-23

申请号：US16921993

申请日：2020-07-07

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Avi Urman ,  Lior Narkis ,  Liron Mula ,  Paraskevas Bakopoulos ,  Ariel Almog ,  Roee Moyal ,  Gal Yefet

IPC: H04B7/26 ,  H04W72/04 ,  H04W74/08 ,  H04L12/931 ,  H04L12/861

Abstract: A network element one or more network ports, network time circuitry and packet processing circuitry. The network ports are configured to communicate with a communication network. The network time circuitry is configured to track a network time defined in the communication network. In some embodiments the packet processing circuitry is configured to receive a definition of one or more timeslots that are synchronized to the network time, and to send outbound packets to the communication network depending on the timeslots. In some embodiments the packet processing circuitry is configured to process inbound. packets, which are received from the communication network, depending on the timeslots.

公开(公告)号：US12182394B2

公开(公告)日：2024-12-31

申请号：US17658292

申请日：2022-04-07

Applicant: Mellanox Technologies, Ltd.

Inventor： Yamin Friedman ,  Idan Burstein ,  Gal Yefet

IPC: G06F3/06

Abstract: A method and system are provided for limiting unnecessary data traffic on the data communication connections connecting various system components, including the various levels of system memory. Some embodiments may include processing a buffer allotment request and/or a buffer release command in coordination with a system or network operation requiring temporary storage of data in a memory buffer. The buffer allotment request may be capable of indicating the amount of storage space required on the memory buffer to execute the system or network operation. The system may be capable of precluding the system or network operation from executing until there is sufficient space in the memory buffer to complete the operation without evicting operational data from the memory buffer. In some embodiments, the buffer release command may signal completion of the system or network operation and release of the utilized memory buffer space for other operations.