公开(公告)号：US11031939B1

公开(公告)日：2021-06-08

申请号：US16823577

申请日：2020-03-19

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Omer Wolkovitz ,  Eilon Yanai

IPC: H03L7/08 ,  H03L7/091

Abstract: A Multi-Chip-Module (MCM) includes an MCM substrate, and at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus including at least first and second embedded-clock data lanes. The DCIC includes a clock-data recovery circuit (CDR) and a data sampler. The CDR is configured to restore a data and a clock from the first data lane, and to output phase correction signaling. The data sampler is configured to restore the data from the second data lane by sampling the second data lane at a phase responsive to the phase correction signaling derived from the first data lane.

公开(公告)号：US11190191B2

公开(公告)日：2021-11-30

申请号：US17246725

申请日：2021-05-03

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Omer Wolkovitz ,  Eilon Yanai

IPC: H03L7/08 ,  H03L7/091

Abstract: A Multi-Chip-Module (MCM) includes an MCM substrate, and at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus including at least first and second embedded-clock data lanes. The DCIC includes a clock-data recovery circuit (CDR) and a data sampler. The CDR is configured to restore a data and a clock from the first data lane, and to output phase correction signaling. The data sampler is configured to restore the data from the second data lane by sampling the second data lane at a phase responsive to the phase correction signaling derived from the first data lane.

公开(公告)号：US20210297082A1

公开(公告)日：2021-09-23

申请号：US17246725

申请日：2021-05-03

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Omer Wolkovitz ,  Eilon Yanai

IPC: H03L7/08 ,  H03L7/091

Abstract: A Multi-Chip-Module (MCM) includes an MCM substrate, and at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus including at least first and second embedded-clock data lanes. The DCIC includes a clock-data recovery circuit (CDR) and a data sampler. The CDR is configured to restore a data and a clock from the first data lane, and to output phase correction signaling. The data sampler is configured to restore the data from the second data lane by sampling the second data lane at a phase responsive to the phase correction signaling derived from the first data lane.