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公开(公告)号:US11711320B2
公开(公告)日:2023-07-25
申请号:US17372555
申请日:2021-07-12
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Sharon Ulman , Eyal Srebro , Shay Aisman
IPC: H04L49/55 , H04L1/1607 , H04L43/0823 , H04L1/20 , H04L43/0852 , H04L1/00 , H04L49/00
CPC classification number: H04L49/555 , H04L1/0061 , H04L1/1628 , H04L1/203 , H04L43/0823 , H04L43/0852 , H04L49/30
Abstract: In one embodiment, a network device, including packet processing circuitry, which includes at least one interface configured to receive packets, and packet forwarding circuitry configured to make respective forwarding decisions for respective ones of the packets, wherein the packet processing circuitry is configured to assign sequence numbers to the packets in at least one stage of packet processing, find missing packets in at least one corresponding later stage of the packet processing responsively to checking for missing sequence numbers among the assigned sequence numbers, and report the missing packets.
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公开(公告)号:US20230168978A1
公开(公告)日:2023-06-01
申请号:US17537543
申请日:2021-11-30
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Sharon Ulman , Eyal Srebro , Shay Aisman
CPC classification number: G06F11/2028 , G06F11/1658 , G06F11/0793 , G06F11/0757 , G06F11/0772
Abstract: A computing apparatus includes a transaction-record memory and a comparator. The transaction-record memory is to receive and store one or more sequences of transaction records, each transaction record including a unique transaction ID and a transaction payload. The comparator is to compare the payloads of transaction records having the same transaction ID, and to initiate a responsive action in response to a discrepancy between the compared transaction payloads.
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公开(公告)号:US20230008730A1
公开(公告)日:2023-01-12
申请号:US17372555
申请日:2021-07-12
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Sharon Ulman , Eyal Srebro , Shay Aisman
IPC: H04L12/939 , H04L1/16 , H04L1/20 , H04L12/26 , H04L1/00
Abstract: In one embodiment, a network device, including packet processing circuitry, which includes at least one interface configured to receive packets, and packet forwarding circuitry configured to make respective forwarding decisions for respective ones of the packets, wherein the packet processing circuitry is configured to assign sequence numbers to the packets in at least one stage of packet processing, find missing packets in at least one corresponding later stage of the packet processing responsively to checking for missing sequence numbers among the assigned sequence numbers, and report the missing packets.
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公开(公告)号:US11899547B2
公开(公告)日:2024-02-13
申请号:US17537543
申请日:2021-11-30
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Sharon Ulman , Eyal Srebro , Shay Aisman
CPC classification number: G06F11/1695 , G06F11/0757 , G06F11/0772 , G06F11/0793 , G06F11/1474 , G06F11/1641 , G06F11/1658 , G06F11/2028
Abstract: A computing apparatus includes a transaction-record memory and a comparator. The transaction-record memory is to receive and store one or more sequences of transaction records, each transaction record including a unique transaction ID and a transaction payload. The comparator is to compare the payloads of transaction records having the same transaction ID, and to initiate a responsive action in response to a discrepancy between the compared transaction payloads.
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