公开(公告)号：US20240152438A1

公开(公告)日：2024-05-09

申请号：US17981508

申请日：2022-11-07

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Alon Singer ,  Ziv Battat ,  Liron Mula

IPC: G06F11/30 ,  G06F11/07 ,  G06F11/34

CPC classification number: G06F11/3037 ,  G06F11/079 ,  G06F11/3075 ,  G06F11/3409

Abstract: An Integrated Circuit (IC) includes one or more functional hardware circuits, one or more processor cores, a cause-tree circuit, a memory buffer, and an analysis circuit. The processor cores are to handle events occurring in the functional hardware circuits. The cause-tree circuit includes leaf nodes, middle nodes and a root node. The leaf nodes are to collect the events from the one or more functional hardware circuits. The middle nodes are to coalesce the collected events and to deliver the events to the root node. The memory buffer is to buffer a plurality of the events delivered to the root node, so as to trigger the processor cores to handle the buffered events. The buffer analysis circuit is to analyze a performance of the cause-tree circuit based on the events buffered in the memory buffer.

公开(公告)号：US11966310B1

公开(公告)日：2024-04-23

申请号：US17981508

申请日：2022-11-07

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Alon Singer ,  Ziv Battat ,  Liron Mula

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F11/3037 ,  G06F11/079 ,  G06F11/3075 ,  G06F11/3409

Abstract: An Integrated Circuit (IC) includes one or more functional hardware circuits, one or more processor cores, a cause-tree circuit, a memory buffer, and an analysis circuit. The processor cores are to handle events occurring in the functional hardware circuits. The cause-tree circuit includes leaf nodes, middle nodes and a root node. The leaf nodes are to collect the events from the one or more functional hardware circuits. The middle nodes are to coalesce the collected events and to deliver the events to the root node. The memory buffer is to buffer a plurality of the events delivered to the root node, so as to trigger the processor cores to handle the buffered events. The buffer analysis circuit is to analyze a performance of the cause-tree circuit based on the events buffered in the memory buffer.