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公开(公告)号:US20240220273A1
公开(公告)日:2024-07-04
申请号:US18527004
申请日:2023-12-01
Applicant: Meta Platforms Technologies, LLC
Inventor: Vignesh Vivekraja , Tomonari Tohara , Reza Tusi , Abuduwaili Tuoheti , Javid Jaffari , Vlad Fruchter , David Vakrat , Ohad Meitav
CPC classification number: G06F9/3893 , G06F9/3001 , G06F9/3012
Abstract: In one embodiment, a system comprising a processor and a non-transitory memory coupled to the processor comprising instructions executable by the processor. The processor, comprising an internal memory; a Multiply-Accumulate (MAC) array; a first vector register array; a second vector register array; and a third vector register array, is operable when executing a first instruction among the instructions to feed a weight vector array from the second vector register array to the MAC array, broadcast an input activation vector to the MAC array, multiply an input activation value broadcast to the MAC unit from the input activation vector and a weight value fed to the MAC unit from the weight vector array at each MAC unit in the MAC array, and store a partial output activation vector to the third vector register array, wherein the partial output activation vector is the output of the MAC array.
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公开(公告)号:US20240193791A1
公开(公告)日:2024-06-13
申请号:US18533916
申请日:2023-12-08
Applicant: Meta Platforms Technologies, LLC
Inventor: Andrey Tovchigrechko , David Vakrat , Olivier Francois Joseph Harel
IPC: G06T7/20
CPC classification number: G06T7/20
Abstract: A method for generating an optical flow for a plurality of successive image frames includes executing an initialization process by performing a plurality of raster scans of a patch of pixels in one or more of the plurality of successive image frames in parallel. The plurality of raster scans of the patch of pixels includes a plurality of optical flow estimates between the plurality of successive image frames. The method includes executing a propagation process based on the plurality of optical flow estimates between the plurality of successive image frames. Executing the propagation process includes propagating the plurality of optical flow estimates for one or more neighboring pixels associated with the patch of pixels. The method includes executing a search process by identifying one or more offsets based on the plurality of optical flow estimates for the one or more neighboring pixels associated with the patch of pixels.
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公开(公告)号:US11601607B2
公开(公告)日:2023-03-07
申请号:US17069709
申请日:2020-10-13
Applicant: META PLATFORMS TECHNOLOGIES, LLC
Inventor: Rajesh Lachhmandas Chhabria , Shuochen Su , Monica Stewart , David Vakrat , Shengqiong Xie , Michael Hall
Abstract: An electronic device includes one or more processors and memory storing instructions for execution by the one or more processors. The stored instructions include instructions for: receiving infrared image information for a three-dimensional area; receiving non-infrared image information for the same three-dimensional area; performing nonlinear intensity adjustment for the received infrared image information; performing nonlinear intensity adjustment for the received non-infrared image information; blending the intensity-adjusted infrared image information and the intensity-adjusted non-infrared image information to obtain a merged image information; and providing the merged image information for determining a depth map. Also disclosed are a corresponding method performed by the electronic device and a computer readable storage medium storing instructions for execution by one or more processors of an electronic device.
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公开(公告)号:US20240220779A1
公开(公告)日:2024-07-04
申请号:US18527063
申请日:2023-12-01
Applicant: Meta Platforms Technologies, LLC
Inventor: Vignesh Vivekraja , Tomonari Tohara , Reza Tusi , Abuduwaili Tuoheti , Javid Jaffari , Vlad Fruchter , David Vakrat , Ohad Meitav
IPC: G06N3/0464 , G06F7/544 , G06F17/15 , H03H17/02
CPC classification number: G06N3/0464 , G06F7/5443 , G06F17/153 , H03H17/02
Abstract: In one embodiment, a system comprising a processor and a non-transitory memory coupled to the processor comprising instructions executable by the processor. The processor, comprising an internal memory; a Multiply-Accumulate (MAC) array; a first vector register array; a second vector register array; and a third vector register array, is operable when executing instructions to transfer weights for M filters and an input activation tensor from an external memory to the internal memory, insert paddings to the input activation tensor in the internal memory based on first configuration parameters, configure the MAC array to a required shape based on second configuration parameters for convolution operations between the input activation tensor and the M filters, and calculate a row of the output activation tensor by performing the convolution operations on corresponding R rows of the input activation tensor with the M filters, wherein R is a filter height.
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公开(公告)号:US20240220255A1
公开(公告)日:2024-07-04
申请号:US18525172
申请日:2023-11-30
Applicant: Meta Platforms Technologies, LLC
Inventor: Reza Tusi , Tomonari Tohara , David Vakrat , Javid Jaffari , Yuan Liu
IPC: G06F9/30
CPC classification number: G06F9/3013 , G06F9/30036
Abstract: In one embodiment, a computing system may set data to a first group of registers. The first group of registers may be configured to be accessed during a single operation cycle. The system may set a number of patterns to a second group of registers. Each pattern of the number of patterns may include an array of index for the data stored in the first group of registers. The system may select, for a first vector register associated with a vector engine, a first pattern from the patterns stored in the second group of registers. The system may load a first portion of the data from the first group of registers to the first vector register based on the first pattern selected for the first vector register from the patterns stored in the second group of registers.
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