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公开(公告)号:US20240276800A1
公开(公告)日:2024-08-15
申请号:US18022754
申请日:2022-03-29
发明人: Qing TANG , Qingsong GU , Lin XIONG , Ning MA , Danfeng WANG
IPC分类号: H10K59/131 , G09G3/3233 , H10K59/124
CPC分类号: H10K59/131 , G09G3/3233 , H10K59/124 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842 , G09G2310/08
摘要: A display substrate includes a base substrate, a pixel circuit layer, a first planarization layer, at least one transparent conductive layer, and a plurality of first light-emitting elements. The base substrate includes a first display region and a second display region, wherein the first display region at least partially surrounds the second display region. The pixel circuit layer is located in the first display region, and includes a plurality of pixel circuits, wherein the plurality of pixel circuits include a plurality of first pixel circuits. A plurality of first light-emitting elements are located in the second display region. The first planarization layer is located on a side of the pixel circuit layer away from the base substrate, and is located in the first display region and the second display region. The transparent conductive layer is located on a side of the first planarization layer away from the base substrate and includes a plurality of first transparent conductive lines and at least one auxiliary structure. The plurality of first light-emitting elements and the plurality of first pixel circuits are coupled through the plurality of first transparent conductive lines. An orthographic projection of the auxiliary structure on the base substrate is overlapped with an orthographic projection of at least one of the pixel circuits on the base substrate.
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公开(公告)号:US20240363065A1
公开(公告)日:2024-10-31
申请号:US18028743
申请日:2022-05-19
发明人: Yuan SHEN , Lin XIONG , Jie TU , Zifeng WANG , Danfeng WANG , Jianmin FAN , Qing TANG
IPC分类号: G09G3/3233 , H10K59/131
CPC分类号: G09G3/3233 , H10K59/131 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/08 , G09G2320/0233 , G09G2320/0247
摘要: A pixel circuit comprises a drive sub-circuit (101), writing sub-circuit (102), reset sub-circuit (103), voltage stabilizing sub-circuit (104), storage sub-circuit (105) and light emitting element. The drive sub-circuit is configured to provide a driving current to the light emitting element under control of signals of a first node (N1) and a second node (N2); the writing sub-circuit is configured to write a signal from a data signal terminal (Data) to N2 under control of signal of a scan signal terminal (Gate); the storage sub-circuit is configured to store a voltage of N1; the voltage stabilizing sub-circuit is configured to stabilize a voltage of an anode terminal of light emitting element through signal of a voltage stabilizing signal terminal (V1); the reset sub-circuit is configured to reset anode terminal of light emitting element under control of signal of Gate and reset N1 under control of signal of a reset control signal terminal (Reset).
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公开(公告)号:US20240212603A1
公开(公告)日:2024-06-27
申请号:US17913428
申请日:2021-10-29
发明人: Yawei ZHU , Xin CAO , Zifeng WANG , Danfeng WANG , Haoyuan FAN
IPC分类号: G09G3/3233
CPC分类号: G09G3/3233 , G09G2300/0426 , G09G2300/0465 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/08 , G09G2320/0233
摘要: A pixel driving circuit, a driving method thereof and a display panel are provided. The pixel driving circuit includes a driving transistor, a capacitor having two terminals connected to a first power terminal and a gate electrode of the driving transistor, and a light emitting device. The pixel driving circuit includes: a reset module; a data writing module; a threshold compensation module including a compensation transistor configured to electrically connect second and gate electrodes of the driving transistor together in the data writing phase; a light emitting control module including a first gating transistor configured to electrically connect the second electrode of the driving transistor and the light emitting device in the reset phase and disconnect the second electrode from the light emitting device in the data writing phase. The compensation transistor and the first gating transistor are oxide transistors, and the driving transistor is a low-temperature polysilicon transistor.
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