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公开(公告)号：US20090176350A1
公开(公告)日：2009-07-09
申请号：US11969272
申请日：2008-01-04
IPC分类号： H01L21/322
CPC分类号： H01L21/3221 , H01L21/265 , H01L29/7833
摘要： A method embodiment deposits a first dielectric layer over a transistor and then implants a gettering agent into the first dielectric layer. After this first dielectric layer is formed, the method forms a second (thicker) dielectric layer over the first dielectric layer. After this, the standard contacts are formed through the insulating layer to the source, drain, gate, etc. of the transistor. Additionally, reactive ion etching, chemical mechanical processing, and other back-end-of-line processing are performed. The back-end-of-line processes can introduce mobile ions into the dielectric over a transistor; however, the gettering agent traps the mobile ions and prevents the mobile ions from contaminating the transistor.
摘要翻译： 方法实施例在晶体管上沉积第一介电层，然后将吸气剂注入第一介电层。 在形成第一介电层之后，该方法在第一介电层上形成第二（较厚的）介电层。 之后，通过绝缘层将晶体管的源极，漏极，栅极等形成标准触点。 此外，执行反应离子蚀刻，化学机械处理和其它后端处理。 后端工艺可以通过晶体管将移动离子引入电介质; 然而，吸气剂捕获移动离子并防止移动离子污染晶体管。
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公开(公告)号：US06800530B2
公开(公告)日：2004-10-05
申请号：US10342420
申请日：2003-01-14
IPC分类号： H01L21336
CPC分类号： H01L29/518 , H01L21/823828 , H01L29/4966 , H01L29/6653 , H01L29/66545 , H01L29/66628
摘要： An integrated circuit employing CMOS technology employs a process integration that combines a source/drain silicide with a replacement gate process using a triple layer hardmask that is consumed during the course of processing in which a first temporary gate sidewall spacer defines an area for the formation of the raised source and drain and a second temporary spacer defines an area for the implant of the source and drain and for the siliciding of the source and drain while the temporary gate is protected from silicidaiton by the hardmask.
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