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    Device having configurable breakpoint based on interrupt status
    2.
    发明授权
    Device having configurable breakpoint based on interrupt status 有权
    设备具有基于中断状态的可配置断点

    公开(公告)号：US09336122B2

    公开(公告)日：2016-05-10

    申请号：US13888370

    申请日：2013-05-07

    Applicant: Microchip Technology Incorporated

    Inventor： Kevin Kilzer ,  Justin Milks ,  Sundar Balasubramanian ,  Thomas Edward Perme ,  Kushala Javagal

    IPC: G06F11/00 ,  G06F11/36

    CPC classification number: G06F11/3636 ,  G06F11/3648

    Abstract: A processor device with debug capabilities has a central processing unit, an interrupt controller, a status unit operable to be set into a first mode indicating an interrupt has occurred or in a second mode indicating normal execution of code, and a debug unit coupled with said status unit and comprising a configurable breakpoint, wherein a condition can be set that a breakpoint is only activated if the device is operating in an interrupt service routine.

    Abstract translation: 具有调试功能的处理器设备具有中央处理单元，中断控制器，状态单元，可操作以将其设置为指示已经发生中断的第一模式，或者指示代码正常执行的第二模式，以及与所述调试单元耦合的调试单元 状态单元并且包括可配置断点，其中可以设置条件，仅当所述设备在中断服务程序中操作时，所述断点才被激活。

    Processor Device with Instruction Trace Capabilities
    3.
    发明申请
    Processor Device with Instruction Trace Capabilities 有权
    具有指令跟踪功能的处理器设备

    公开(公告)号：US20130318408A1

    公开(公告)日：2013-11-28

    申请号：US13888357

    申请日：2013-05-06

    Applicant: Microchip Technology Incorporated

    Inventor： Kevin Kilzer ,  Justin Milks ,  Sundar Balasubramanian ,  Thomas Edward Perme ,  Kushala Javagal

    IPC: G01R31/3177

    CPC classification number: G01R31/3177 ,  G06F11/3636 ,  G06F11/3648

    Abstract: A processor device with debug capabilities has a central processing unit, debug circuitry including a trace module and an external interface, wherein the trace module generates a trace stream including information about executed instructions, wherein the trace stream is output through the external interface, and wherein the trace module is further operable to detect a trigger signal and upon detection to insert a trace packet into the generated trace stream.

    Abstract translation: 具有调试功能的处理器设备具有中央处理单元，调试电路，包括跟踪模块和外部接口，其中所述跟踪模块生成包括关于所执行指令的信息的跟踪流，其中所述跟踪流通过所述外部接口输出，并且其中 跟踪模块还可操作以检测触发信号，并且在检测到时将跟踪包插入到生成的跟踪流中。

    Processor device with instruction trace capabilities
    4.
    发明授权
    Processor device with instruction trace capabilities 有权
    具有指令跟踪功能的处理器设备

    公开(公告)号：US09377507B2

    公开(公告)日：2016-06-28

    申请号：US13888357

    申请日：2013-05-06

    Applicant: Microchip Technology Incorporated

    Inventor： Kevin Kilzer ,  Justin Milks ,  Sundar Balasubramanian ,  Thomas Edward Perme ,  Kushala Javagal

    IPC: G06F11/00 ,  G01R31/3177 ,  G06F11/36

    CPC classification number: G01R31/3177 ,  G06F11/3636 ,  G06F11/3648

    Abstract: A processor device with debug capabilities has a central processing unit, debug circuitry including a trace module and an external interface, wherein the trace module generates a trace stream including information about executed instructions, wherein the trace stream is output through the external interface, and wherein the trace module is further operable to detect a trigger signal and upon detection to insert a trace packet into the generated trace stream.

    Abstract translation: 具有调试功能的处理器设备具有中央处理单元，调试电路，包括跟踪模块和外部接口，其中所述跟踪模块生成包括关于所执行指令的信息的跟踪流，其中所述跟踪流通过所述外部接口输出，并且其中 跟踪模块还可操作以检测触发信号，并且在检测到时将跟踪包插入到生成的跟踪流中。

    Device Having Configurable Breakpoint Based on Interrupt Status
    5.
    发明申请
    Device Having Configurable Breakpoint Based on Interrupt Status 有权
    具有基于中断状态的可配置断点的器件

    公开(公告)号：US20130297975A1

    公开(公告)日：2013-11-07

    申请号：US13888370

    申请日：2013-05-07

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED

    Inventor： Kevin Kilzer ,  Justin Milks ,  Sundar Balasubramanian ,  Thomas Edward Perme ,  Kushala Javagal

    IPC: G06F11/36

    CPC classification number: G06F11/3636 ,  G06F11/3648

    Abstract: A processor device with debug capabilities has a central processing unit, an interrupt controller, a status unit operable to be set into a first mode indicating an interrupt has occurred or in a second mode indicating normal execution of code, and a debug unit coupled with said status unit and comprising a configurable breakpoint, wherein a condition can be set that a breakpoint is only activated if the device is operating in an interrupt service routine.

    Abstract translation: 具有调试功能的处理器设备具有中央处理单元，中断控制器，状态单元，可操作以将其设置为指示已经发生中断的第一模式，或者指示代码正常执行的第二模式，以及与所述调试单元耦合的调试单元 状态单元并且包括可配置断点，其中可以设置条件，仅当所述设备在中断服务程序中操作时，所述断点才被激活。

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