公开(公告)号：US20170017584A1

公开(公告)日：2017-01-19

申请号：US15209467

申请日：2016-07-13

Applicant: Microchip Technology Incorporated

Inventor： Kevin Kilzer ,  Shyamsunder Ramanathan ,  Sai Karthik Rajaraman ,  Justin Milks

IPC: G06F13/10 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/102 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/4068 ,  G06F13/4282 ,  G06F13/4291

Abstract: A synchronous serial peripheral device has a transmission unit coupled with a data output line and a clock unit coupled with a clock line. The serial peripheral device transmits a minimum of a single transmission, wherein in a first operating mode the transmission unit and the clock unit are configurable to perform a data transmission with a data length that can be defined to be between one (1) and eight (8) bit.

Abstract translation: 同步串行外围设备具有与数据输出线耦合的传输单元和与时钟线耦合的时钟单元。 串行外围设备发送最少的单个传输，其中在第一操作模式中，传输单元和时钟单元可配置为执行具有数据长度的数据传输，数据长度可以被定义在1（1）到8（ 8）位。

公开(公告)号：US20170168981A1

公开(公告)日：2017-06-15

申请号：US15373391

申请日：2016-12-08

Applicant: Microchip Technology Incorporated

Inventor： Kevin Kilzer ,  Shyamsunder Ramanathan ,  Sai Karthik Rajaraman ,  Justin Milks

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/364

CPC classification number: G06F13/4282 ,  G06F13/364 ,  G06F13/404 ,  G06F13/4291

Abstract: A serial peripheral interface (SPI) module includes a transceiver including a clock line, a data line and at least one slave select line. The module also includes an interface circuit configured to monitor the slave select line and assert a fault based upon an incorrect de-assertion of the slave select line.

公开(公告)号：US09298570B2

公开(公告)日：2016-03-29

申请号：US13888367

申请日：2013-05-07

Applicant: Microchip Technology Incorporated

Inventor： Justin Milks ,  Thomas Edward Perme ,  Sundar Balasubramanian ,  Kushala Javagal

IPC: G06F11/00 ,  G06F11/26 ,  G06F11/36

CPC classification number: G06F11/26 ,  G06F11/3636 ,  G06F11/3656

Abstract: A processor device with debug capabilities has a central processing unit, debug circuitry including a trace module, a system clock module for providing internal clock signals, and a reset detection unit which during a debug mode prevents the system clock module from receiving a reset signal.

Abstract translation: 具有调试功能的处理器设备具有中央处理单元，包括跟踪模块的调试电路，用于提供内部时钟信号的系统时钟模块以及在调试模式期间防止系统时钟模块接收复位信号的复位检测单元。

公开(公告)号：US20180121380A1

公开(公告)日：2018-05-03

申请号：US15498846

申请日：2017-04-27

Applicant: Microchip Technology Incorporated

Inventor： Sean Steedman ,  Kevin Kilzer ,  Ashish Senapati ,  Justin Milks ,  Prashanth Pulipaka

IPC: G06F13/362 ,  G06F13/26 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F13/362 ,  G06F13/26 ,  G06F13/28 ,  G06F13/34 ,  G06F13/4068

Abstract: A programmable system arbiter for granting access to a system bus among a plurality of arbiter clients and a central processing unit is disclosed. The programmable system arbiter may include one or more interrupt priority registers, each of the one or more interrupt priority registers associated with an interrupt type; and system arbitration logic operable to arbitrate access to the system bus among the plurality of arbiter clients and the CPU based at least on an analysis of a programmed priority order, the programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of a plurality of operating modes of the central processing unit, and each of the one or more interrupt types.

公开(公告)号：US20170168980A1

公开(公告)日：2017-06-15

申请号：US15373219

申请日：2016-12-08

Applicant: Microchip Technology Incorporated

Inventor： Kevin Kilzer ,  Shyamsunder Ramanathan ,  Sai Karthik Rajaraman ,  Justin Milks

IPC: G06F13/42 ,  G06F1/10

CPC classification number: G06F13/4282 ,  G06F1/10 ,  G06F13/4291

Abstract: A serial peripheral interface (SPI) module, comprising a transceiver, the transceiver including a clock line, a data line and at least one slave select line. The SPI also comprises an interface circuit configured to operate in an automatic slave select mode, wherein the interface circuit is configured to automatically assert the slave select line at least one clock before a first clock edge is generated.

公开(公告)号：US10114776B2

公开(公告)日：2018-10-30

申请号：US15498846

申请日：2017-04-27

Applicant: Microchip Technology Incorporated

Inventor： Sean Steedman ,  Kevin Kilzer ,  Ashish Senapati ,  Justin Milks ,  Prashanth Pulipaka

IPC: G06F13/36 ,  G06F13/00 ,  G06F13/362 ,  G06F13/26 ,  G06F13/28 ,  G06F13/40 ,  G06F13/34

Abstract: A programmable system arbiter for granting access to a system bus among a plurality of arbiter clients and a central processing unit is disclosed. The programmable system arbiter may include one or more interrupt priority registers, each of the one or more interrupt priority registers associated with an interrupt type; and system arbitration logic operable to arbitrate access to the system bus among the plurality of arbiter clients and the CPU based at least on an analysis of a programmed priority order, the programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of a plurality of operating modes of the central processing unit, and each of the one or more interrupt types.

公开(公告)号：US09336122B2

公开(公告)日：2016-05-10

申请号：US13888370

申请日：2013-05-07

Applicant: Microchip Technology Incorporated

Inventor： Kevin Kilzer ,  Justin Milks ,  Sundar Balasubramanian ,  Thomas Edward Perme ,  Kushala Javagal

IPC: G06F11/00 ,  G06F11/36

CPC classification number: G06F11/3636 ,  G06F11/3648

Abstract: A processor device with debug capabilities has a central processing unit, an interrupt controller, a status unit operable to be set into a first mode indicating an interrupt has occurred or in a second mode indicating normal execution of code, and a debug unit coupled with said status unit and comprising a configurable breakpoint, wherein a condition can be set that a breakpoint is only activated if the device is operating in an interrupt service routine.

Abstract translation: 具有调试功能的处理器设备具有中央处理单元，中断控制器，状态单元，可操作以将其设置为指示已经发生中断的第一模式，或者指示代码正常执行的第二模式，以及与所述调试单元耦合的调试单元 状态单元并且包括可配置断点，其中可以设置条件，仅当所述设备在中断服务程序中操作时，所述断点才被激活。

公开(公告)号：US20130318408A1

公开(公告)日：2013-11-28

申请号：US13888357

申请日：2013-05-06

Applicant: Microchip Technology Incorporated

Inventor： Kevin Kilzer ,  Justin Milks ,  Sundar Balasubramanian ,  Thomas Edward Perme ,  Kushala Javagal

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G06F11/3636 ,  G06F11/3648

Abstract: A processor device with debug capabilities has a central processing unit, debug circuitry including a trace module and an external interface, wherein the trace module generates a trace stream including information about executed instructions, wherein the trace stream is output through the external interface, and wherein the trace module is further operable to detect a trigger signal and upon detection to insert a trace packet into the generated trace stream.

Abstract translation: 具有调试功能的处理器设备具有中央处理单元，调试电路，包括跟踪模块和外部接口，其中所述跟踪模块生成包括关于所执行指令的信息的跟踪流，其中所述跟踪流通过所述外部接口输出，并且其中 跟踪模块还可操作以检测触发信号，并且在检测到时将跟踪包插入到生成的跟踪流中。

公开(公告)号：US09377507B2

公开(公告)日：2016-06-28

申请号：US13888357

申请日：2013-05-06

Applicant: Microchip Technology Incorporated

Inventor： Kevin Kilzer ,  Justin Milks ,  Sundar Balasubramanian ,  Thomas Edward Perme ,  Kushala Javagal

IPC: G06F11/00 ,  G01R31/3177 ,  G06F11/36

CPC classification number: G01R31/3177 ,  G06F11/3636 ,  G06F11/3648

Abstract: A processor device with debug capabilities has a central processing unit, debug circuitry including a trace module and an external interface, wherein the trace module generates a trace stream including information about executed instructions, wherein the trace stream is output through the external interface, and wherein the trace module is further operable to detect a trigger signal and upon detection to insert a trace packet into the generated trace stream.

Abstract translation: 具有调试功能的处理器设备具有中央处理单元，调试电路，包括跟踪模块和外部接口，其中所述跟踪模块生成包括关于所执行指令的信息的跟踪流，其中所述跟踪流通过所述外部接口输出，并且其中 跟踪模块还可操作以检测触发信号，并且在检测到时将跟踪包插入到生成的跟踪流中。

公开(公告)号：US20130297975A1

公开(公告)日：2013-11-07

申请号：US13888370

申请日：2013-05-07

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： Kevin Kilzer ,  Justin Milks ,  Sundar Balasubramanian ,  Thomas Edward Perme ,  Kushala Javagal

IPC: G06F11/36

CPC classification number: G06F11/3636 ,  G06F11/3648

Abstract: A processor device with debug capabilities has a central processing unit, an interrupt controller, a status unit operable to be set into a first mode indicating an interrupt has occurred or in a second mode indicating normal execution of code, and a debug unit coupled with said status unit and comprising a configurable breakpoint, wherein a condition can be set that a breakpoint is only activated if the device is operating in an interrupt service routine.

Abstract translation: 具有调试功能的处理器设备具有中央处理单元，中断控制器，状态单元，可操作以将其设置为指示已经发生中断的第一模式，或者指示代码正常执行的第二模式，以及与所述调试单元耦合的调试单元 状态单元并且包括可配置断点，其中可以设置条件，仅当所述设备在中断服务程序中操作时，所述断点才被激活。