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公开(公告)号：US20130326127A1
公开(公告)日：2013-12-05
申请号：US13959365
申请日：2013-08-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Giuseppe Ferrari , Pracolo Carannante , Angelo Di Sena , Fabio Salvati , Anna Sorgente
IPC: G06F12/02
CPC classification number: G06F12/0238 , G06F3/0617 , G06F12/0246 , G06F12/0866 , G06F2212/2022 , G06F2212/222
Abstract: Subject matter disclosed herein relates to sub-block accessible cache memory.
Abstract translation: 本文公开的主题涉及子块可访问高速缓冲存储器。
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Patent Agency Ranking
公开(公告)号：US20150127892A1
公开(公告)日：2015-05-07
申请号：US14536333
申请日：2014-11-07
Applicant: Micron Technology, Inc.
Inventor： Procolo Carannante , Angelo Di Sena , Fabio Salvati , Giuseppe Ferrari , Anna Sorgente
IPC: G06F12/02
CPC classification number: G06F12/0246 , G06F2212/7207 , G06F2212/7211 , Y02D10/13
Abstract: A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.
Abstract translation: 一种方法包括通过将数据从第一存储器阵列的第一部分复制到第一存储器阵列的第二部分来应对磨损级操作请求，以及将与数据相关联的数据从第二存储器阵列的第三部分复制到 第二存储器阵列的第四部分。 第一存储器阵列包括NAND或基于NAND的存储器阵列，并且第二存储器阵列包括非易失性存储器，其包括由以下组成的组中的至少一个：相变存储器，EEPROM和NOR闪存。
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公开(公告)号：US08924638B2
公开(公告)日：2014-12-30
申请号：US13857943
申请日：2013-04-05
Applicant: Micron Technology, Inc.
Inventor： Procolo Carannante , Angelo Di Sena , Fabio Salvati , Giuseppe Ferrari , Anna Sorgente
CPC classification number: G06F12/0246 , G06F2212/7207 , G06F2212/7211 , Y02D10/13
Abstract: A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.
Abstract translation: 一种方法包括通过将数据从第一存储器阵列的第一部分复制到第一存储器阵列的第二部分来应对磨损级操作请求，以及将与数据相关联的数据从第二存储器阵列的第三部分复制到 第二存储器阵列的第四部分。 第一存储器阵列包括NAND或基于NAND的存储器阵列，并且第二存储器阵列包括非易失性存储器，其包括由以下组成的组中的至少一个：相变存储器，EEPROM和NOR闪存。
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公开(公告)号：US08782345B2
公开(公告)日：2014-07-15
申请号：US13959365
申请日：2013-08-05
Applicant: Micron Technology, Inc.
Inventor： Giuseppe Ferrari , Procolo Carannante , Angelo Di Sena , Fabio Salvati , Anna Sorgente
CPC classification number: G06F12/0238 , G06F3/0617 , G06F12/0246 , G06F12/0866 , G06F2212/2022 , G06F2212/222
Abstract: Subject matter disclosed herein relates to sub-block accessible cache memory.
Abstract translation: 本文公开的主题涉及子块可访问高速缓冲存储器。
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公开(公告)号：US09152559B2
公开(公告)日：2015-10-06
申请号：US14536333
申请日：2014-11-07
Applicant: Micron Technology, Inc.
Inventor： Procolo Carannante , Angelo Di Sena , Fabio Salvati , Giuseppe Ferrari , Anna Sorgente
CPC classification number: G06F12/0246 , G06F2212/7207 , G06F2212/7211 , Y02D10/13
Abstract: A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.
Abstract translation: 一种方法包括通过将数据从第一存储器阵列的第一部分复制到第一存储器阵列的第二部分来应对磨损级操作请求，以及将与数据相关联的数据从第二存储器阵列的第三部分复制到 第二存储器阵列的第四部分。 第一存储器阵列包括NAND或基于NAND的存储器阵列，并且第二存储器阵列包括非易失性存储器，其包括由以下组成的组中的至少一个：相变存储器，EEPROM和NOR闪存。
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公开(公告)号：US20130227206A1
公开(公告)日：2013-08-29
申请号：US13857943
申请日：2013-04-05
Applicant: Micron Technology, Inc.
Inventor： Procolo Carannante , Angelo Di Sena , Fabio Salvati , Giuseppe Ferrari , Anna Sorgente
IPC: G06F12/02
CPC classification number: G06F12/0246 , G06F2212/7207 , G06F2212/7211 , Y02D10/13
Abstract: A method includes responding to a wear-level operation request by copying data from a first portion of a first memory array to a second portion of the first memory array, and copying metadata associated with the data from a third portion of a second memory array to a fourth portion of the second memory array. The first memory array includes a NAND or NAND-based memory array, and the second memory array includes non-volatile memory including at least one of the group consisting of: phase-change memory, EEPROM, and NOR flash memory.
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