公开(公告)号：US11804281B2

公开(公告)日：2023-10-31

申请号：US17450582

申请日：2021-10-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Donald M. Morgan ,  Alan J. Wilson ,  Bryan D. Kerstetter ,  John D. Porter

IPC: G06F11/00 ,  G11C29/00 ,  G06F11/16 ,  G06F11/18

CPC classification number: G11C29/70 ,  G06F11/16 ,  G06F11/1666 ,  G06F11/18

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for automatic soft post-package repair (ASPPR). A memory may receive a row address along with a signal indicating an ASPPR operation, such as a bad page flag being set. A word line engine generates a physical address based on the row address, and ASPPR registers stores the physical address. The time it takes from receiving the row address to storing the physical address may be within the timing of an access operation on the memory such as tRAS. The row address may specify a single page of information. If the bad page flag is set, then a subsequent PPR operation may blow fuses to encode the physical address stored in the ASPPR registers.

公开(公告)号：US20240370176A1

公开(公告)日：2024-11-07

申请号：US18653300

申请日：2024-05-02

Applicant: Micron Technology, Inc.

Inventor： Bryan D. Kerstetter ,  Alan J. Wilson ,  Donald M. Morgan

IPC: G06F3/06

Abstract: Systems, methods, and apparatuses are provided for wear leveling repair in a memory device. A host is configured to issue a wear leveling command and a repair request to a memory device configured to check source data in a memory of the memory device for errors in response to receiving the wear leveling command from the host, transfer source data in the memory of the memory device to a target page, and repair a source page if the source data includes an error. The memory device is further configured to set a new repair match if a wear leveling repair element was not consumed after receiving the repair request and flush a previous repair match before setting the new repair match if the wear leveling repair element was consumed and a physical address of an incoming repair request is associated with the wear leveling repair element.

公开(公告)号：US20240281368A1

公开(公告)日：2024-08-22

申请号：US18439437

申请日：2024-02-12

Applicant: Micron Technology, Inc.

Inventor： Bryan D. Kerstetter ,  Donald M. Morgan

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7211

Abstract: Systems, methods, and apparatuses are provided for periodic and activity-based memory management. A memory management bank can be coupled to a memory management block, wherein the memory management bank includes a plurality of memory banks. Each memory bank of the plurality of memory banks includes an activate counter to increment responsive to the memory bank receiving an activate command and circuitry to determine whether a value of the activate counter is equal to or greater than a wear leveling threshold and perform a wear leveling operation on data stored in the memory bank responsive to determining the value of the activate counter is equal to or greater than the wear leveling threshold.

公开(公告)号：US20230116534A1

公开(公告)日：2023-04-13

申请号：US17450582

申请日：2021-10-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Donald M. Morgan ,  Alan J. Wilson ,  Bryan D. Kerstetter ,  John D. Porter

IPC: G11C29/00

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for automatic soft post-package repair (ASPPR). A memory may receive a row address along with a signal indicating an ASPPR operation, such as a bad page flag being set. A word line engine generates a physical address based on the row address, and ASPPR registers stores the physical address. The time it takes from receiving the row address to storing the physical address may be within the timing of an access operation on the memory such as tRAS. The row address may specify a single page of information. If the bad page flag is set, then a subsequent PPR operation may blow fuses to encode the physical address stored in the ASPPR registers.