公开(公告)号：US20250053327A1

公开(公告)日：2025-02-13

申请号：US18806210

申请日：2024-08-15

Applicant: Micron Technology, Inc.

Inventor： Alan J. Wilson ,  Donald M. Morgan

IPC: G06F3/06 ,  G06F12/10

Abstract: Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.

公开(公告)号：US20230010619A1

公开(公告)日：2023-01-12

申请号：US17932206

申请日：2022-09-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi ,  Donald M. Morgan

IPC: G11C11/4078 ,  G11C11/408 ,  G11C11/406

Abstract: Apparatuses, systems, and methods for dynamically allocated aggressor detection. A memory may include an aggressor address storage structure which tracks access patterns to row addresses and their associated bank addresses. These may be used to determine if a row and bank address received as part of an access operation are an aggressor row and bank address. The aggressor row address may be used to generate a refresh address for a bank identified by the aggressor bank address. Since the aggressor storage structure tracks both row and bank addresses, its storage space may be dynamically allocated between banks based on access patterns to those banks.

公开(公告)号：US20220291854A1

公开(公告)日：2022-09-15

申请号：US17197733

申请日：2021-03-10

Applicant: Micron Technology, Inc.

Inventor： Alan J. Wilson ,  Donald M. Morgan

IPC: G06F3/06 ,  G06F12/10

Abstract: Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.

公开(公告)号：US20220230672A1

公开(公告)日：2022-07-21

申请号：US17153555

申请日：2021-01-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sujeet Ayyapureddi ,  Donald M. Morgan

IPC: G11C11/4078 ,  G11C11/406 ,  G11C11/408

Abstract: Apparatuses, systems, and methods for dynamically allocated aggressor detection. A memory may include an aggressor address storage structure which tracks access patterns to row addresses and their associated bank addresses. These may be used to determine if a row and bank address received as part of an access operation are an aggressor row and bank address. The aggressor row address may be used to generate a refresh address for a bank identified by the aggressor bank address. Since the aggressor storage structure tracks both row and bank addresses, its storage space may be dynamically allocated between banks based on access patterns to those banks.

公开(公告)号：US10354714B2

公开(公告)日：2019-07-16

申请号：US15245067

申请日：2016-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Donald M. Morgan

IPC: G11C11/406 ,  G11C11/4076 ,  G11C7/04

Abstract: Systems and apparatuses for memory devices utilizing a continuous self-refresh timer are provided. An example apparatus includes a self-refresh timer configured to generate a signal periodically, wherein a period of the signal is based on a self-refresh refresh time interval, wherein the self-refresh refresh time interval is dependent on temperature information. The apparatus may further include a memory bank comprising at least a first subarray and in communication with a first subarray refresh circuit, which may include a first refresh status counter. The first refresh status counter may be in communication with the self-refresh timer and configured to receive the signal from the self-refresh timer, change a count value of the first refresh status counter in a first direction each time the signal is received, and change the count value of the first refresh status counter in a second direction each time the first subarray is refreshed.

公开(公告)号：US20190172521A1

公开(公告)日：2019-06-06

申请号：US16259052

申请日：2019-01-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Donald M. Morgan

IPC: G11C11/406 ,  G11C29/50 ,  G11C29/02 ,  G11C11/4076 ,  G11C29/00 ,  G11C11/408

Abstract: Apparatuses and methods for detecting refresh starvation at a memory. An example apparatus, may include a plurality of memory cells, and a control circuit configured to monitor refresh request commands and to perform an action that prevents unauthorized access to data stored at the plurality of memory cells in response to detection that timing of the refresh request commands has failed to meet a refresh timing limit.

公开(公告)号：US20180373850A1

公开(公告)日：2018-12-27

申请号：US15633045

申请日：2017-06-26

Applicant: Micron Technology, Inc.

Inventor： Donald M. Morgan ,  Joseph C. Sher

IPC: G06F21/14 ,  G06F12/14

Abstract: Data obfuscation is generally discussed herein. In one or more embodiments, a memory circuit can include a storage portion including entries with corresponding addresses, one or more of the entries configured to include data stored thereon, and processing circuitry to read first data from a first entry of the entries, alter the first data by at least one of: (1) flipping one or more bits of the first data, (2) scrambling two or more bits of the first data, and (3) altering an address of the first data, and write the altered first data to the storage portion.

公开(公告)号：US09378791B2

公开(公告)日：2016-06-28

申请号：US14800512

申请日：2015-07-15

Applicant: Micron Technology, Inc.

Inventor： Donald M. Morgan ,  Jongtae Kwak ,  Jeffrey P. Wright

IPC: G11C7/22 ,  G11C7/10 ,  H03K19/00

CPC classification number: G11C7/222 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/109 ,  H03K19/0005

Abstract: Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command detection circuit configured to detect whether a next write command is received within a consecutive write command period of a current write command responsive to the current write command provided at an output of the write command register. The example apparatus further includes a clock signal control circuit coupled to the consecutive write command detection circuit and configured to control a clock signal to an input/output (I/O) latch based on whether the consecutive write command detection circuit detects that the next write command is within the consecutive write command period.

公开(公告)号：US12062407B2

公开(公告)日：2024-08-13

申请号：US17823740

申请日：2022-08-31

Applicant: Micron Technology, Inc.

Inventor： Alan John Wilson ,  Donald M. Morgan ,  John David Porter

IPC: G11C29/54 ,  G11C29/00

CPC classification number: G11C29/76 ,  G11C29/54 ,  G11C29/808

Abstract: Apparatus and methods for page-based soft post package repair are disclosed. Based on data stored in a storage element, an address may be decoded to a prime row, a row-based redundant row, or a page-based redundant row. A match logic circuit may determine whether the address corresponds to a defective prime row and generate a match signal. A decoder can select a redundant row to be accessed instead of a prime row in response to the match signal indicating that the address data corresponding to the address to be accessed matches defective address data stored in a volatile memory. A page-based redundant row allows for page-by-page substitution for defective memory, allowing functional portions of memory to continue to be used.

公开(公告)号：US11804281B2

公开(公告)日：2023-10-31

申请号：US17450582

申请日：2021-10-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Donald M. Morgan ,  Alan J. Wilson ,  Bryan D. Kerstetter ,  John D. Porter

IPC: G06F11/00 ,  G11C29/00 ,  G06F11/16 ,  G06F11/18

CPC classification number: G11C29/70 ,  G06F11/16 ,  G06F11/1666 ,  G06F11/18

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for automatic soft post-package repair (ASPPR). A memory may receive a row address along with a signal indicating an ASPPR operation, such as a bad page flag being set. A word line engine generates a physical address based on the row address, and ASPPR registers stores the physical address. The time it takes from receiving the row address to storing the physical address may be within the timing of an access operation on the memory such as tRAS. The row address may specify a single page of information. If the bad page flag is set, then a subsequent PPR operation may blow fuses to encode the physical address stored in the ASPPR registers.