REPAIR OPERATION TECHNIQUES
    1.
    发明申请

    公开(公告)号:US20250053327A1

    公开(公告)日:2025-02-13

    申请号:US18806210

    申请日:2024-08-15

    Abstract: Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.

    APPARATUSES AND METHODS FOR DYNAMICALLY ALLOCATED AGGRESSOR DETECTION

    公开(公告)号:US20230010619A1

    公开(公告)日:2023-01-12

    申请号:US17932206

    申请日:2022-09-14

    Abstract: Apparatuses, systems, and methods for dynamically allocated aggressor detection. A memory may include an aggressor address storage structure which tracks access patterns to row addresses and their associated bank addresses. These may be used to determine if a row and bank address received as part of an access operation are an aggressor row and bank address. The aggressor row address may be used to generate a refresh address for a bank identified by the aggressor bank address. Since the aggressor storage structure tracks both row and bank addresses, its storage space may be dynamically allocated between banks based on access patterns to those banks.

    REPAIR OPERATION TECHNIQUES
    3.
    发明申请

    公开(公告)号:US20220291854A1

    公开(公告)日:2022-09-15

    申请号:US17197733

    申请日:2021-03-10

    Abstract: Methods, systems, and devices for repair operation techniques are described. A memory device may detect a failure of a read operation associated with a physical row address of a memory die. The memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. Additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. The memory device may send a command or other information to perform a repair operation for the physical row address. The memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.

    APPARATUSES AND METHODS FOR DYNAMICALLY ALLOCATED AGGRESSOR DETECTION

    公开(公告)号:US20220230672A1

    公开(公告)日:2022-07-21

    申请号:US17153555

    申请日:2021-01-20

    Abstract: Apparatuses, systems, and methods for dynamically allocated aggressor detection. A memory may include an aggressor address storage structure which tracks access patterns to row addresses and their associated bank addresses. These may be used to determine if a row and bank address received as part of an access operation are an aggressor row and bank address. The aggressor row address may be used to generate a refresh address for a bank identified by the aggressor bank address. Since the aggressor storage structure tracks both row and bank addresses, its storage space may be dynamically allocated between banks based on access patterns to those banks.

    Temperature-dependent refresh circuit configured to increase or decrease a count value of a refresh timer according to a self-refresh signal

    公开(公告)号:US10354714B2

    公开(公告)日:2019-07-16

    申请号:US15245067

    申请日:2016-08-23

    Inventor: Donald M. Morgan

    Abstract: Systems and apparatuses for memory devices utilizing a continuous self-refresh timer are provided. An example apparatus includes a self-refresh timer configured to generate a signal periodically, wherein a period of the signal is based on a self-refresh refresh time interval, wherein the self-refresh refresh time interval is dependent on temperature information. The apparatus may further include a memory bank comprising at least a first subarray and in communication with a first subarray refresh circuit, which may include a first refresh status counter. The first refresh status counter may be in communication with the self-refresh timer and configured to receive the signal from the self-refresh timer, change a count value of the first refresh status counter in a first direction each time the signal is received, and change the count value of the first refresh status counter in a second direction each time the first subarray is refreshed.

    MEMORY SYSTEM INCLUDING DATA OBFUSCATION
    7.
    发明申请

    公开(公告)号:US20180373850A1

    公开(公告)日:2018-12-27

    申请号:US15633045

    申请日:2017-06-26

    Abstract: Data obfuscation is generally discussed herein. In one or more embodiments, a memory circuit can include a storage portion including entries with corresponding addresses, one or more of the entries configured to include data stored thereon, and processing circuitry to read first data from a first entry of the entries, alter the first data by at least one of: (1) flipping one or more bits of the first data, (2) scrambling two or more bits of the first data, and (3) altering an address of the first data, and write the altered first data to the storage portion.

    Memory device with redundancy for page-based repair

    公开(公告)号:US12062407B2

    公开(公告)日:2024-08-13

    申请号:US17823740

    申请日:2022-08-31

    CPC classification number: G11C29/76 G11C29/54 G11C29/808

    Abstract: Apparatus and methods for page-based soft post package repair are disclosed. Based on data stored in a storage element, an address may be decoded to a prime row, a row-based redundant row, or a page-based redundant row. A match logic circuit may determine whether the address corresponds to a defective prime row and generate a match signal. A decoder can select a redundant row to be accessed instead of a prime row in response to the match signal indicating that the address data corresponding to the address to be accessed matches defective address data stored in a volatile memory. A page-based redundant row allows for page-by-page substitution for defective memory, allowing functional portions of memory to continue to be used.

Patent Agency Ranking