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公开(公告)号：US20240362114A1
公开(公告)日：2024-10-31
申请号：US18607152
申请日：2024-03-15
发明人： Jaeil Kim , Donald M. Morgan , Alan J. Wilson
IPC分类号： G06F11/10
CPC分类号： G06F11/1068 , G06F11/1016
摘要： A system for providing memory management holding latch placement and control signal generation is disclosed. The system performs memory management operations on a memory device to reduce memory cell wear and tear and to balance use of the memory cells of the memory device. The system separates memory management read operations from memory management write operations by utilizing a holding register that stores data from a source memory cell prior to transfer to a target memory cell. When a memory management read operation is initiated, data and error correction parity bits from the source memory cell are provided to a circuit including the holding register. The data and parity bits are analyzed for errors and the errors are corrected prior to storing the data and parity bits into the holding register. The data and associated parity bits are then transferred from the holding register to the target memory cell.
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公开(公告)号：US12086425B2
公开(公告)日：2024-09-10
申请号：US17730755
申请日：2022-04-27
IPC分类号： G06F3/06
CPC分类号： G06F3/0622 , G06F3/0604 , G06F3/0652 , G06F3/0659 , G06F3/0679
摘要： Methods, systems, and devices for techniques for non-volatile data protection are described. As part of a power on operation, a non-volatile memory system may be configured to selectively stored data. For example, the memory system may determine whether a host system is authorized to access data stored in the memory system prior to a power off operation. If the memory system determines that the host system is authorized, the memory device may retain the data. If the memory system determines that the host system is not authorized, the memory system may erase all or a portion of the data. In some cases, the memory system may maintain a retain flag to determine whether the host system is authorized. Additionally or alternatively, the memory system may determine whether a password received from the host system is valid to determine whether the host system is authorized.
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公开(公告)号：US20210335443A1
公开(公告)日：2021-10-28
申请号：US17317221
申请日：2021-05-11
摘要： Methods, systems, and devices for modifying memory bank operating parameters are described. Operating parameter(s) may be individually adjusted for memory banks or memory bank groups within a memory system based on trimming information. The local trimming information for a memory bank or memory bank group may be stored in a fuse set that also stores repair information for the particular memory bank or in a fuse set that also stores repair information for a memory bank in the particular memory bank group. The local trimming information may be applied to operating parameters for particular memory banks or memory bank groups relative to or instead of global adjustments applied to operating parameters of multiple or all of the memory banks in the memory system.
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公开(公告)号：US11145387B2
公开(公告)日：2021-10-12
申请号：US17062264
申请日：2020-10-02
发明人： Alan J. Wilson
IPC分类号： G11C29/00 , G11C29/02 , G11C29/32 , G11C17/18 , G11C11/408 , G11C7/22 , G11C7/10 , G11C11/4076 , G11C29/44
摘要： Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled.
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公开(公告)号：US11011250B2
公开(公告)日：2021-05-18
申请号：US16805049
申请日：2020-02-28
摘要： Methods, systems, and devices for modifying memory bank operating parameters are described. Operating parameter(s) may be individually adjusted for memory banks or memory bank groups within a memory system based on trimming information. The local trimming information for a memory bank or memory bank group may be stored in a fuse set that also stores repair information for the particular memory bank or in a fuse set that also stores repair information for a memory bank in the particular memory bank group. The local trimming information may be applied to operating parameters for particular memory banks or memory bank groups relative to or instead of global adjustments applied to operating parameters of multiple or all of the memory banks in the memory system.
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公开(公告)号：US10909011B2
公开(公告)日：2021-02-02
申请号：US16161932
申请日：2018-10-16
发明人： Alan J. Wilson
摘要： Techniques are provided for storing a row address of a defective row of memory cells to a bank of non-volatile storage elements (e.g., fuses or anti-fuses). After a memory device has been packaged, one or more rows of memory cells may become defective. In order to repair (e.g., replace) the rows, a post-package repair (PPR) operation may occur to replace the defective row with a redundant row of the memory array. To replace the defective row with a redundant row, an address of the defective row may be stored (e.g., mapped) to an available bank of non-volatile storage elements that is associated with a redundant row. Based on the bank of non-volatile storage elements the address of the defective row, subsequent access operations may utilize the redundant row and not the defective row.
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公开(公告)号：US20200243158A1
公开(公告)日：2020-07-30
申请号：US16256796
申请日：2019-01-24
发明人： Alan J. Wilson
IPC分类号： G11C29/00 , G11C29/02 , G11C29/32 , G11C17/18 , G11C11/408 , G11C11/4076 , G11C7/22 , G11C7/10
摘要： Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled.
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公开(公告)号：US10403390B1
公开(公告)日：2019-09-03
申请号：US15948585
申请日：2018-04-09
发明人： Alan J. Wilson , John E. Riley
摘要： Systems and methods to perform post-packaging repair of previously repaired data groups are disclosed. The devices may have an array of addressable rows or columns of memory cells, which can be activated. Upon identification of defect in a memory cell row or column, a repair in which the memory cell may be deactivated and a secondary row may be activated in its place may be performed. Volatile and non-volatile storage elements may be used to store the defective memory addresses. Logic circuitry in the device may match a requested address with the stored addresses and generate logic signals that trigger activation of a repaired row in place of the defective row or column. Moreover, defective rows or columns that have been previously repaired once may be further repaired. To that end, logic circuitry implementing a trumping mechanism may be used to prevent activation of multiple data rows or columns for addresses that were repaired multiple times.
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公开(公告)号：US12118211B2
公开(公告)日：2024-10-15
申请号：US18100803
申请日：2023-01-24
IPC分类号： G06F3/06
CPC分类号： G06F3/0604 , G06F3/0644 , G06F3/0679
摘要： Methods, systems, and devices for retiring pages of a memory device are described. An ordered set of device information pages may be used to store device information. The device information pages may be in non-volatile memory. Each page may include a counter value of the number of accesses to indicate if the page includes valid data. A flag associated with the page may be set when the counter value reaches a threshold, to retire the page. Upon power-up, the device may determine which page to use, based on the flags. The flag may be stored in the page, or may be separate (e.g., fuse elements). If fuse elements are used, the page may store a programming-in-process flag to indicate when programming of the fuse element may not have been completed before power loss, in which case the programming may be restarted after power is restored.
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公开(公告)号：US12112831B2
公开(公告)日：2024-10-08
申请号：US17877592
申请日：2022-07-29
CPC分类号： G11C7/24 , G11C7/1063 , G11C7/1066 , G11C8/20
摘要： Methods, systems, and devices for memory row-hammer mitigation are described. A memory device may operate based on a scheme that is continuous across power cycles. For example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region if a value of the counter satisfies the threshold value. Upon transitioning power states, the value of the counter may be stored to a non-volatile memory such that it may be accessed when transitioning back to the original power state (e.g., an “ON” state). Accordingly, the value of the counter may be maintained across power cycles.
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