公开(公告)号：US20240231617A1

公开(公告)日：2024-07-11

申请号：US18612028

申请日：2024-03-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoharu Tanaka ,  Huai-Yuan Tseng ,  Dung V. Nguyen ,  Kishore Kumar Muchherla ,  Eric N. Lee ,  Akira Goda ,  James Fitzpatrick ,  Dave Ebsen

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0679

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

公开(公告)号：US20240311036A1

公开(公告)日：2024-09-19

申请号：US18606742

申请日：2024-03-15

Applicant: Micron Technology, Inc.

Inventor： Daniel J. Hubbard ,  Kishore K. Muchherla ,  Dave Ebsen ,  Akira Goda

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0688

Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells. Each string of the plurality of strings comprises: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. The first erase block can be configured as a first zone of one or more zones corresponding to a namespace independently of the second erase block.

公开(公告)号：US11960722B2

公开(公告)日：2024-04-16

申请号：US17872217

申请日：2022-07-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoharu Tanaka ,  Huai-Yuan Tseng ,  Dung V. Nguyen ,  Kishore Kumar Muchherla ,  Eric N. Lee ,  Akira Goda ,  James Fitzpatrick ,  Dave Ebsen

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0679

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

公开(公告)号：US20240028200A1

公开(公告)日：2024-01-25

申请号：US17872217

申请日：2022-07-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoharu Tanaka ,  Huai-Yuan Tseng ,  Dung V. Nguyen ,  Kishore Kumar Muchherla ,  Eric N. Lee ,  Akira Goda ,  James Fitzpatrick ,  Dave Ebsen

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0679

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.