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    Two-tier defect scan management
    1.
    发明授权
    Two-tier defect scan management 有权

    公开(公告)号：US12105967B2

    公开(公告)日：2024-10-01

    申请号：US17894794

    申请日：2022-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Robert Loren O. Ursua ,  Sead Zildzic ,  Eric N. Lee ,  Jonathan S. Parry ,  Lakshmi Kalpana K. Vakati ,  Jeffrey S. McNeil

    IPC: G06F3/06

    CPC classification number: G06F3/0629 ,  G06F3/0625 ,  G06F3/0679

    Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

    SINGLE-LEVEL CELL PROGRAM-VERIFY, LATCH-LIMITED DATA RECOVERY
    5.
    发明公开
    SINGLE-LEVEL CELL PROGRAM-VERIFY, LATCH-LIMITED DATA RECOVERY 审中-公开

    公开(公告)号：US20230352107A1

    公开(公告)日：2023-11-02

    申请号：US18128463

    申请日：2023-03-30

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Tomoko Ogura Iwasaki

    IPC: G11C29/52 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C29/52

    Abstract: Control logic in a memory device identifies memory cells of a memory array configured as single-level cell (SLC) memory, where the memory cells include two or more memory cells programmed during a program phase and associated with a selected wordline of the memory array. The control logic further causes a program verify voltage to be applied to the selected wordline during a ganged SLC verify operation to be performed concurrently on the memory cells. In response to the memory cells failing to pass ganged SLC verify operation, the control logic further: copies first data, which is associated with a first memory cell, into the data recovery latch; causes a program verify operation to be performed separately on the first memory cell; and in response to the first memory cell reaching a program verify voltage, causes an inhibit of the first memory cell from further programming.

    DATA BURST SUSPEND MODE USING PAUSE DETECTION
    6.
    发明公开
    DATA BURST SUSPEND MODE USING PAUSE DETECTION 审中-公开

    公开(公告)号：US20230289307A1

    公开(公告)日：2023-09-14

    申请号：US18119578

    申请日：2023-03-09

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Leonid Minz ,  Yoav Weinberg ,  Ali Feiz Zarrin Ghalam ,  Luigi Pilolli

    IPC: G06F13/30 ,  G06F13/16

    CPC classification number: G06F13/30 ,  G06F13/1668

    Abstract: Operations include monitoring a logical level of a first pin of the plurality of pins while a data burst is active, wherein the first pin is associated with at least one of a read enable signal or a data strobe signal, determining whether a period of time during which the logical level of the first pin is held at a first logical level satisfies a threshold condition, in response to determining that the period of time satisfies the threshold condition, continuing to monitor the logical level of the first pin, determining whether the logical level of the first pin changed from the first logical level to a second logical level, and in response to determining that the logical level of the first pin changed from the first logical to the second logical level, causing warmup cycles to be performed.

    Memory devices for multiple read operations
    7.
    发明授权
    Memory devices for multiple read operations 有权

    公开(公告)号：US11756594B2

    公开(公告)日：2023-09-12

    申请号：US17463789

    申请日：2021-09-01

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Eric N. Lee ,  Kishore Kumar Muchherla ,  Jeffrey S. McNeil ,  Jung-Sheng Hoei

    IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C7/14

    CPC classification number: G11C7/106 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/14 ,  G11C7/222

    Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.

    Cache release command for cache reads in a memory sub-system
    8.
    发明授权
    Cache release command for cache reads in a memory sub-system 有权

    公开(公告)号：US11669456B2

    公开(公告)日：2023-06-06

    申请号：US17452764

    申请日：2021-10-28

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Yoav Weinberg

    IPC: G06F12/00 ,  G06F12/0882 ,  G06F12/0817 ,  G06F9/30 ,  G06F12/0891

    CPC classification number: G06F12/0882 ,  G06F9/30047 ,  G06F9/30101 ,  G06F12/0828 ,  G06F12/0891

    Abstract: A memory device includes a page cache comprising a cache register, a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a cache release command indicating that data associated with a first subset of the plurality of memory planes and pertaining to a previous read command was received by the requestor. Responsive to the cache release command, the control logic returns to the requestor, data from the cache register and associated with a second subset of the plurality of memory planes and pertaining to the previous read command, while concurrently copying data associated with the first subset of the plurality of memory planes and pertaining to a subsequent read command into the cache register.

    MEMORY DEVICE INCLUDING DYNAMIC PROGRAMMING VOLTAGE
    10.
    发明申请
    MEMORY DEVICE INCLUDING DYNAMIC PROGRAMMING VOLTAGE 有权

    公开(公告)号：US20220351787A1

    公开(公告)日：2022-11-03

    申请号：US17745415

    申请日：2022-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Lawrence Celso Miranda

    IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30

    Abstract: Some embodiments include apparatus and methods using access lines, first memory cells coupled to an access line of the access lines, and a control unit including circuitry. The control unit is configured to apply a first voltage to the access line; check first threshold voltages of the first memory cells after applying the first voltage; obtain offset information based on a determination that at least one of the first threshold voltages is greater than a selected voltage; generate a second voltage, the second voltage being a function of the first voltage and the offset information; and apply the second voltage to one of the access lines during an operation of storing information in second memory cells.

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