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    MEMORY DEVICE SENSORS
    1.
    发明公开
    MEMORY DEVICE SENSORS 审中-公开

    公开(公告)号：US20240036629A1

    公开(公告)日：2024-02-01

    申请号：US18379440

    申请日：2023-10-12

    Applicant: Micron Technology, Inc.

    Inventor： Debra M. Bell ,  Roya Baghi ,  Erica M. Gove ,  Zahra Hosseinimakarem ,  Cheryl M. O'Donnell

    IPC: G06F1/3234 ,  G11C16/26 ,  G11C11/56

    CPC classification number: G06F1/3275 ,  G11C16/26 ,  G11C11/5642

    Abstract: Systems, apparatuses, and methods related to using memory device sensors are described. Some memory system or device types include sensors embedded in their circuitry. For instance, a device can be coupled to a memory device with an embedded sensor. The memory device can transmit the data generated by the embedded sensor using a sensor output coupled to the device. The memory device may generate, based at least in part on a characteristic of a memory device, a signal from a sensor embedded in the memory device and transmit the signal generated by the sensor from the memory device to another device coupled to the memory device.

    Semiconductor device with modified access and associated methods and systems
    4.
    发明授权
    Semiconductor device with modified access and associated methods and systems 有权

    公开(公告)号：US11687403B2

    公开(公告)日：2023-06-27

    申请号：US17350099

    申请日：2021-06-17

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Jannusch ,  Brett K. Dodds ,  Debra M. Bell ,  Joshua E. Alzheimer ,  Scott E. Smith

    IPC: G11C29/00 ,  G06F11/10

    CPC classification number: G06F11/1044 ,  G06F11/102 ,  G06F11/1032

    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.

    CONDITIONAL ROW ACTIVATION AND ACCESS DURING REFRESH FOR MEMORY DEVICES AND ASSOCIATED METHODS AND SYSTEMS
    6.
    发明申请
    CONDITIONAL ROW ACTIVATION AND ACCESS DURING REFRESH FOR MEMORY DEVICES AND ASSOCIATED METHODS AND SYSTEMS 有权

    公开(公告)号：US20220172771A1

    公开(公告)日：2022-06-02

    申请号：US17107306

    申请日：2020-11-30

    Applicant: Micron Technology, Inc.

    Inventor： Miles S. Wiscombe ,  Debra M. Bell ,  Brian T. Pecha ,  Vaughn N. Johnson ,  Kyle Alexander

    IPC: G11C11/406 ,  G11C11/408

    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to conditionally activate certain rows during refresh operations such that the memory devices can execute operations directed to the activated rows concurrently with the refresh operations. In some embodiments, the memory device receives an activate (ACT) command directed to a section of a memory bank while performing refresh operations for the memory bank. The memory device may carry out the ACT command if certain conditions are satisfied not to corrupt the data being refreshed. Subsequently, the memory device generates a signal to indicate the ACT command has been accepted to activate a row identified by the ACT command. Further, the memory device can perform subsequent access commands directed to the row, in parallel with the refresh operations.

    Refresh-related activation improvements
    7.
    发明授权
    Refresh-related activation improvements 有权

    公开(公告)号：US11282562B2

    公开(公告)日：2022-03-22

    申请号：US17159706

    申请日：2021-01-27

    Applicant: Micron Technology, Inc.

    Inventor： Stephen Michael Kaminski ,  Anthony D. Veches ,  James S. Rehmeyer ,  Debra M. Bell ,  Dale Herber Hiscock ,  Joshua E. Alzheimer

    IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4091

    Abstract: Methods, systems, and devices for refresh-related activation in memory are described. A memory device may conduct a refresh operation to preserve the integrity of data. A refresh operation may be associated with a refresh time where the memory device is unable to execute or issue any commands (e.g., access commands). By posting (e.g., saving) one or more commands and/or row addresses during the refresh time, the memory device may be configured to execute the saved commands and/or re-open one or more rows associated with the saved row addresses at a later time (e.g., upon completion of the refresh operation). Accordingly, fewer commands may be issued to activate the memory cells after the refresh time.

    Semiconductor device with word line degradation monitor and associated methods and systems
    8.
    发明授权
    Semiconductor device with word line degradation monitor and associated methods and systems 有权

    公开(公告)号：US11270757B2

    公开(公告)日：2022-03-08

    申请号：US17022030

    申请日：2020-09-15

    Applicant: Micron Technology, Inc.

    Inventor： Gitanjali T. Ghosh ,  Debra M. Bell ,  Arunmozhi R. Subramaniam ,  Roya Baghi ,  Deepika Thumsi Umesh ,  Sue-Fern Ng

    IPC: G11C11/408 ,  G11C11/4099 ,  G11C11/4076 ,  G11C11/4074

    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor degradations in word line characteristics. The memory device may generate a reference signal in response to an access command directed to a memory array including a plurality of word lines, in some embodiments. The memory array may include a victim word line configured to accumulate adverse effects of executing multiple access commands at the word lines of the memory array. When the degradation in the word line characteristics causes reliability issues (e.g., corrupted data), the memory array is deemed unreliable, and may be blocked from memory operations. The memory device may compare the reference signal and a signal from the victim word line to determine whether preventive measures may be appropriate to avoid (or mitigate) such reliability issues.

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