公开(公告)号：US20140281182A1

公开(公告)日：2014-09-18

申请号：US13838296

申请日：2013-03-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Graziano Mirichigni ,  Daniele Balluchi ,  Lucas Porzio

IPC: G06F3/06

CPC classification number: G06F13/1689 ,  G06F13/161 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/22 ,  G11C8/06 ,  G11C2207/2209 ,  G11C2207/2272 ,  G11C2207/229

Abstract: Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to receive an activate command indicative of a type of a command during a first addressing phase and to receive the command during a second addressing phase. The memory may further be configured to provide information indicating that the memory is not available to perform a command responsive, at least in part, to receiving the command during a variable latency period and to provide information indicating that the memory is available to perform a command responsive, at least in part, to receiving the command after the variable latency period.

Abstract translation: 本文公开了用于可变延迟存储器操作的装置和方法。 示例性装置可以包括被配置为在第一寻址阶段期间接收指示命令类型的激活命令并在第二寻址阶段期间接收命令的存储器。 存储器还可以被配置为提供指示存储器不可用于执行命令的信息，所述信息至少部分地响应于在可变等待时间段期间接收命令并且提供指示存储器可用于执行命令的信息 至少部分地响应于在可变潜伏期之后接收命令。