公开(公告)号：US12182024B2

公开(公告)日：2024-12-31

申请号：US18508141

申请日：2023-11-13

Applicant: Micron Technology, Inc.

Inventor： Muthazhagan Balasubramani ,  Venkatesh Anandpadmanabhan

IPC: G06F12/0862

Abstract: A system and method for a memory sub-system to reduce latency by prefetching data blocks and preloading them into host memory of a host system. An example system including a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request of a host system to access a data block in the memory device; determining the data block stored in a first buffer in host memory is related to a set of one or more data blocks stored at the memory device; and storing the set of one or more data blocks in a second buffer in the host memory, wherein the first buffer is controlled by the host system and the second buffer is controlled by a memory sub-system.

公开(公告)号：US12131073B2

公开(公告)日：2024-10-29

申请号：US18522726

申请日：2023-11-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Muthazhagan Balasubramani ,  Woei Chen Peh

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/0679

Abstract: A set of submission queues associated with a host system is identified. A first set of internal queues and a second set of internal queues is generated based on the set of submission queues. Responsive to fetching a first memory access command pending in a submission queue of the set of submission queues, a first internal queue of the first set of internal queues is populated. Responsive to processing the first memory access command from the first internal queue of the first set of internal queues, a second internal queue of the second set of internal queues is populated. Responsive to completion of the first memory access command from the second internal queue of the second set of internal queues, an indication of the completion of the first memory access command is returned to the host system.

公开(公告)号：US20240094958A1

公开(公告)日：2024-03-21

申请号：US18522726

申请日：2023-11-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Muthazhagan Balasubramani ,  Woei Chen Peh

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/0679

Abstract: A set of submission queues associated with a host system is identified. A first set of internal queues and a second set of internal queues is generated based on the set of submission queues. Responsive to fetching a first memory access command pending in a submission queue of the set of submission queues, a first internal queue of the first set of internal queues is populated. Responsive to processing the first memory access command from the first internal queue of the first set of internal queues, a second internal queue of the second set of internal queues is populated. Responsive to completion of the first memory access command from the second internal queue of the second set of internal queues, an indication of the completion of the first memory access command is returned to the host system.

公开(公告)号：US20250013393A1

公开(公告)日：2025-01-09

申请号：US18892718

申请日：2024-09-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Muthazhagan Balasubramani ,  Woei Chen Peh

IPC: G06F3/06

Abstract: A set of submission queues associated with a host system is identified. A first set of internal queues and a second set of internal queues is generated based on the set of submission queues. Responsive to fetching a first memory access command pending in a submission queue of the set of submission queues, a first internal queue of the first set of internal queues is populated. Responsive to processing the first memory access command from the first internal queue of the first set of internal queues, a second internal queue of the second set of internal queues is populated. Responsive to completion of the first memory access command from the second internal queue of the second set of internal queues, an indication of the completion of the first memory access command is returned to the host system.

公开(公告)号：US11868660B2

公开(公告)日：2024-01-09

申请号：US17720868

申请日：2022-04-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Muthazhagan Balasubramani ,  Woei Chen Peh

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/0679

Abstract: A set of submission queues associated with a host system is identified. A first set of internal queues and a second set of internal queues is generated based on the set of submission queues. Responsive to fetching a first memory access command pending in a submission queue of the set of submission queues, a first internal queue of the first set of internal queues is populated. Responsive to processing the first memory access command from the first internal queue of the first set of internal queues, a second internal queue of the second set of internal queues is populated. Responsive to completion of the first memory access command from the second internal queue of the second set of internal queues, an indication of the completion of the first memory access command is returned to the host system.

公开(公告)号：US12204795B2

公开(公告)日：2025-01-21

申请号：US17890781

申请日：2022-08-18

Applicant: Micron Technology, Inc.

Inventor： Muthazhagan Balasubramani

IPC: G06F3/06 ,  G06F11/08

Abstract: A host submits a command to a memory device, where a host status indicator (ID) for the host and a memory device status ID for the memory device are assigned with the command in at least one of a status command slot related to the command. An interrupt signal asserted during processing of the command is determined, where the interrupt signal is indicative of a change in at least one of the host status ID and the memory device status ID. After determining that the interrupt signal is asserted at least one of the host status ID and the memory device status ID are read. Based on the read information, a failure in at least one of the host and device is corrected prior to initiation of a timeout process.

公开(公告)号：US20230333776A1

公开(公告)日：2023-10-19

申请号：US17720868

申请日：2022-04-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Muthazhagan Balasubramani ,  Woei Chen Peh

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0635 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0679

Abstract: A set of submission queues associated with a host system is identified. A first set of internal queues and a second set of internal queues is generated based on the set of submission queues. Responsive to fetching a first memory access command pending in a submission queue of the set of submission queues, a first internal queue of the first set of internal queues is populated. Responsive to processing the first memory access command from the first internal queue of the first set of internal queues, a second internal queue of the second set of internal queues is populated. Responsive to completion of the first memory access command from the second internal queue of the second set of internal queues, an indication of the completion of the first memory access command is returned to the host system.

公开(公告)号：US20250147700A1

公开(公告)日：2025-05-08

申请号：US19015190

申请日：2025-01-09

Applicant: Micron Technology, Inc.

Inventor： Muthazhagan Balasubramani

IPC: G06F3/06 ,  G06F11/08

Abstract: A host submits a command to a memory device, where a host status indicator (ID) for the host and a memory device status ID for the memory device are assigned with the command in at least one of a status command slot related to the command. An interrupt signal asserted during processing of the command is determined, where the interrupt signal is indicative of a change in at least one of the host status ID and the memory device status ID. After determining that the interrupt signal is asserted at least one of the host status ID and the memory device status ID are read. Based on the read information, a failure in at least one of the host and device is corrected prior to initiation of a timeout process.

公开(公告)号：US20240061614A1

公开(公告)日：2024-02-22

申请号：US17890781

申请日：2022-08-18

Applicant: Micron Technology, Inc.

Inventor： Muthazhagan Balasubramani

IPC: G06F3/06 ,  G06F11/08

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F11/08

Abstract: A host submits a command to a memory device, where a host status indicator (ID) for the host and a memory device status ID for the memory device are assigned with the command in at least one of a status command slot related to the command. An interrupt signal asserted during processing of the command is determined, where the interrupt signal is indicative of a change in at least one of the host status ID and the memory device status ID. After determining that the interrupt signal is asserted at least one of the host status ID and the memory device status ID are read. Based on the read information, a failure in at least one of the host and device is corrected prior to initiation of a timeout process.

公开(公告)号：US11816035B2

公开(公告)日：2023-11-14

申请号：US17557406

申请日：2021-12-21

Applicant: Micron Technology, Inc.

Inventor： Muthazhagan Balasubramani ,  Venkatesh Anandpadmanabhan

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/1024 ,  G06F2212/6022

Abstract: A system and method for a memory sub-system to reduce latency by prefetching data blocks and preloading them into host memory of a host system. An example system including a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request of a host system to access a data block in the memory device; transmitting a response to the host system that indicates the data block is stored in a first buffer in host memory; determining the data block is related to a set of one or more data blocks stored at the memory device; and storing the set of one or more data blocks in a second buffer in the host memory, wherein the first buffer is controlled by the host system and the second buffer is controlled by a memory sub-system.