公开(公告)号：US11468923B2

公开(公告)日：2022-10-11

申请号：US16924023

申请日：2020-07-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tsugio Takahashi ,  Zer Liang

IPC: G11C7/10

Abstract: Apparatuses, mufti-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

公开(公告)号：US20200027495A1

公开(公告)日：2020-01-23

申请号：US16543168

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Tsugio Takahashi

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4096

Abstract: An apparatus may include a first data strobe (DQS) output buffer (OB), a second DQS OB and control logic. The first data strobe (DQS) output buffer (OB) and the second DQS OB are each coupled to a DQS terminal. The first DQS OB and the second DQS OB are configured to provide a DQS signal to the DQS terminal responsive to a read clock signal. The control logic is configured to receive the read clock signal to control the first DQS OB and the second DQS OB. The apparatus is configured to selectively prevent the control logic from receiving the read clock signal while the DQS signal is being provided to the DQS terminal.

公开(公告)号：US10573371B2

公开(公告)日：2020-02-25

申请号：US16543168

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Tsugio Takahashi

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C11/408

Abstract: An apparatus may include a first data strobe (DQS) output buffer (OB), a second DQS OB and control logic. The first data strobe (DQS) output buffer (OB) and the second DQS OB are each coupled to a DQS terminal. The first DQS OB and the second DQS OB are configured to provide a DQS signal to the DQS terminal responsive to a read clock signal. The control logic is configured to receive the read clock signal to control the first DQS OB and the second DQS OB. The apparatus is configured to selectively prevent the control logic from receiving the read clock signal while the DQS signal is being provided to the DQS terminal.

公开(公告)号：US20170287531A1

公开(公告)日：2017-10-05

申请号：US15626915

申请日：2017-06-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tsugio Takahashi ,  Zer Liang

IPC: G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/1003

Abstract: Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

公开(公告)号：US09715909B2

公开(公告)日：2017-07-25

申请号：US13804461

申请日：2013-03-14

Applicant: Micron Technology, Inc.

Inventor： Tsugio Takahashi ,  Zer Liang

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/1003

Abstract: Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configure d to delay receipt of the column control signals to the memory.

公开(公告)号：US10109327B2

公开(公告)日：2018-10-23

申请号：US15626915

申请日：2017-06-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tsugio Takahashi ,  Zer Liang

IPC: G11C7/00 ,  G11C7/10

Abstract: Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

公开(公告)号：US20140269121A1

公开(公告)日：2014-09-18

申请号：US13804461

申请日：2013-03-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tsugio Takahashi ,  Zer Liang

IPC: G11C7/22

CPC classification number: G11C7/1039 ,  G11C7/1003

Abstract: Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

Abstract translation: 公开了一种用于控制多存储器系统中的数据定时的装置，多存储器系统和方法。 示例性装置包括多个存储单元。 在示例性装置中，多个存储单元的存储单元包括被配置为基于行控制信号和列控制信号向数据流水线提供相关联的读取数据的存储器。 存储器单元还包括被配置为将行控制信号和列控制信号提供给存储器的本地控制逻辑，以及耦合在本地控制逻辑和存储器之间的可配置延迟电路，其被配置为将列控制信号的接收延迟到 记忆。

公开(公告)号：US20200342920A1

公开(公告)日：2020-10-29

申请号：US16924023

申请日：2020-07-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tsugio Takahashi ,  Zer Liang

IPC: G11C7/10

Abstract: Apparatuses, mufti-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

公开(公告)号：US10748584B2

公开(公告)日：2020-08-18

申请号：US16136068

申请日：2018-09-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tsugio Takahashi ,  Zer Liang

IPC: G11C7/10

Abstract: Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.

公开(公告)号：US10431293B1

公开(公告)日：2019-10-01

申请号：US16042924

申请日：2018-07-23

Applicant: Micron Technology, Inc.

Inventor： Tsugio Takahashi

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4096

Abstract: An apparatus may include a first data strobe (DQS) output buffer (OB), a second DQS OB and control logic. The first data strobe (DQS) output buffer (OB) and the second DQS OB are each coupled to a DQS terminal. The first DQS OB and the second DQS OB are configured to provide a DQS signal to the DQS terminal responsive to a read clock signal. The control logic is configured to receive the read clock signal to control the first DQS OB and the second DQS OB. The apparatus is configured to selectively prevent the control logic from receiving the read clock signal while the DQS signal is being provided to the DQS terminal.