公开(公告)号：US20250069636A1

公开(公告)日：2025-02-27

申请号：US18939609

申请日：2024-11-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yankang He ,  Walter Di Francesco ,  Luca Nubile ,  Chang Siau

IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4094

Abstract: One example of a memory device includes an array of flash memory cells, an array of Dynamic Random Access Memory (DRAM) memory cells, and a controller. The controller is configured to execute first instructions stored in the array of DRAM memory cells to access the array of flash memory cells.

公开(公告)号：US20230377626A1

公开(公告)日：2023-11-23

申请号：US17747183

申请日：2022-05-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yankang He ,  Walter Di Francesco ,  Luca Nubile ,  Chang Siau

IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4094

CPC classification number: G11C11/40611 ,  G11C11/40622 ,  G11C11/4072 ,  G11C11/4094

Abstract: One example of a memory device includes an array of flash memory cells, an array of Dynamic Random Access Memory (DRAM) memory cells, and a controller. The controller is configured to execute first instructions stored in the array of DRAM memory cells to access the array of flash memory cells.

公开(公告)号：US12165688B2

公开(公告)日：2024-12-10

申请号：US17747183

申请日：2022-05-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yankang He ,  Walter Di Francesco ,  Luca Nubile ,  Chang Siau

IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4094

Abstract: One example of a memory device includes an array of flash memory cells, an array of Dynamic Random Access Memory (DRAM) memory cells, and a controller. The controller is configured to execute first instructions stored in the array of DRAM memory cells to access the array of flash memory cells.

公开(公告)号：US20240241643A1

公开(公告)日：2024-07-18

申请号：US18407239

申请日：2024-01-08

Applicant: Micron Technology, Inc.

Inventor： Biagio Iorio ,  Luca Nubile ,  Walter Di Francesco ,  Jeremy Binfet ,  Liang Yu ,  Yankang He ,  Ali Mohammadzadeh

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679

Abstract: Control logic on a memory die of a multi-die memory sub-system receives, from a memory sub-system controller, a data burst command indicating an upcoming data burst event and determines an expected current utilization in the memory sub-system during the data burst event. The control logic further determines whether the expected current utilization in the memory sub-system during the data burst event satisfies a threshold criterion and responsive to determining that the expected current utilization in the memory sub-system during the data burst event does not satisfy the threshold criterion, pauses one or more operations being executed by the control logic on the memory die until the expected current utilization in the memory sub-system during the data burst event satisfies the threshold criterion. Responsive to determining that the expected current utilization in the memory sub-system during the data burst event satisfies the threshold criterion, the control logic provides, to the memory sub-system controller, an indication that the data burst event is approved and can perform one or more operations corresponding to the data burst event.