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    INTERNAL CLOCK SIGNALING
    1.
    发明公开
    INTERNAL CLOCK SIGNALING 审中-公开

    公开(公告)号：US20240241673A1

    公开(公告)日：2024-07-18

    申请号：US18622132

    申请日：2024-03-29

    Applicant: Micron Technology, Inc.

    Inventor： Liang Yu ,  Luigi Pilolli ,  Biagio Iorio

    IPC: G06F3/06 ,  G06F1/04 ,  G06F1/3234

    CPC classification number: G06F3/0659 ,  G06F1/04 ,  G06F3/0604 ,  G06F3/0679 ,  G06F1/3275

    Abstract: A method includes selecting a particular ready/busy pin (R/B#) among a plurality of R/B# pins that are associated with respective memory dice among a plurality of memory dice of a memory device. The method further includes receiving, by at least one memory dice among the plurality of memory dice, signaling indicative of performance of a memory access while the particular R/B# pin is set to low, and, initiating an internal clocking signal subsequent to receipt of the signaling indicative of performance of the memory access, wherein the internal clocking signal is associated with timing of operations performed by the plurality of memory dice.

    DUAL DATA CHANNEL PEAK POWER MANAGEMENT
    4.
    发明公开
    DUAL DATA CHANNEL PEAK POWER MANAGEMENT 审中-公开

    公开(公告)号：US20240143501A1

    公开(公告)日：2024-05-02

    申请号：US18494841

    申请日：2023-10-26

    Applicant: Micron Technology, Inc.

    Inventor： Luca Nubile ,  Luigi Pilolli ,  Liang Yu ,  Ali Mohammadzadeh ,  Walter Di Francesco ,  Biagio Iorio

    IPC: G06F12/02 ,  G06F1/28

    CPC classification number: G06F12/0246 ,  G06F1/28

    Abstract: A memory device includes a plurality of memory dies. Each memory die of the plurality of memory dies includes a memory die and control logic, operatively coupled with the memory die, to perform operations including receiving, during a current auxiliary data communication cycle, a token to enable auxiliary data communication, in response to receiving the token, determining whether to communicate auxiliary data via an auxiliary data channel to at least one other memory die of a plurality of memory dies, and in response to determining to communicate the auxiliary data via the auxiliary data channel to the at least one other memory die, causing the auxiliary data to be communicated to the at least one other memory die.

    INTERNAL CLOCK SIGNALING
    5.
    发明申请
    INTERNAL CLOCK SIGNALING 有权

    公开(公告)号：US20230060310A1

    公开(公告)日：2023-03-02

    申请号：US17464868

    申请日：2021-09-02

    Applicant: Micron Technology, Inc.

    Inventor： Liang Yu ,  Luigi Pilolli ,  Biagio Iorio

    IPC: G06F3/06 ,  G06F1/04

    Abstract: A method includes selecting a particular ready/busy pin (R/B#) among a plurality of R/B# pins that are associated with respective memory dice among a plurality of memory dice of a memory device. The method further includes receiving, by at least one memory dice among the plurality of memory dice, signaling indicative of performance of a memory access while the particular R/B# pin is set to low, and, initiating an internal clocking signal subsequent to receipt of the signaling indicative of performance of the memory access, wherein the internal clocking signal is associated with timing of operations performed by the plurality of memory dice.

    CURRENT MANAGEMENT DURING DATA BURST OPERATIONS IN A MULTI-DIE MEMORY DEVICE
    8.
    发明公开
    CURRENT MANAGEMENT DURING DATA BURST OPERATIONS IN A MULTI-DIE MEMORY DEVICE 审中-公开

    公开(公告)号：US20240241643A1

    公开(公告)日：2024-07-18

    申请号：US18407239

    申请日：2024-01-08

    Applicant: Micron Technology, Inc.

    Inventor： Biagio Iorio ,  Luca Nubile ,  Walter Di Francesco ,  Jeremy Binfet ,  Liang Yu ,  Yankang He ,  Ali Mohammadzadeh

    IPC: G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679

    Abstract: Control logic on a memory die of a multi-die memory sub-system receives, from a memory sub-system controller, a data burst command indicating an upcoming data burst event and determines an expected current utilization in the memory sub-system during the data burst event. The control logic further determines whether the expected current utilization in the memory sub-system during the data burst event satisfies a threshold criterion and responsive to determining that the expected current utilization in the memory sub-system during the data burst event does not satisfy the threshold criterion, pauses one or more operations being executed by the control logic on the memory die until the expected current utilization in the memory sub-system during the data burst event satisfies the threshold criterion. Responsive to determining that the expected current utilization in the memory sub-system during the data burst event satisfies the threshold criterion, the control logic provides, to the memory sub-system controller, an indication that the data burst event is approved and can perform one or more operations corresponding to the data burst event.

    Prioritized power budget arbitration for multiple concurrent memory access operations
    9.
    发明授权
    Prioritized power budget arbitration for multiple concurrent memory access operations 有权

    公开(公告)号：US11977748B2

    公开(公告)日：2024-05-07

    申请号：US17668311

    申请日：2022-02-09

    Applicant: Micron Technology, Inc.

    Inventor： Luca Nubile ,  Walter Di Francesco ,  Fumin Gu ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Liang Yu

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

    Abstract: A memory device includes memory dice, each memory die including: a memory array; a memory to store a data structure; and control logic that includes: multiple processing threads to execute memory access operations on the memory array concurrently; a priority ring counter, the data structure to store an association between a value of the priority ring counter and a subset of the multiple processing threads; a threads manager to increment the value of the priority ring counter before a power management cycle and to identify one or more prioritized processing threads corresponding to the subset of the multiple processing threads; and a peak power manager coupled with the threads manager and to prioritize allocation of power to the one or more prioritized processing threads during the power management cycle.

    Memory dice internal clock
    10.
    发明授权
    Memory dice internal clock 有权

    公开(公告)号：US11960764B2

    公开(公告)日：2024-04-16

    申请号：US17464868

    申请日：2021-09-02

    Applicant: Micron Technology, Inc.

    Inventor： Liang Yu ,  Luigi Pilolli ,  Biagio Iorio

    IPC: G06F1/04 ,  G06F1/3234 ,  G06F3/06

    CPC classification number: G06F3/0659 ,  G06F1/04 ,  G06F3/0604 ,  G06F3/0679 ,  G06F1/3275

    Abstract: A method includes selecting a particular ready/busy pin (R/B #) among a plurality of R/B # pins that are associated with respective memory dice among a plurality of memory dice of a memory device. The method further includes receiving, by at least one memory dice among the plurality of memory dice, signaling indicative of performance of a memory access while the particular R/B # pin is set to low, and, initiating an internal clocking signal subsequent to receipt of the signaling indicative of performance of the memory access, wherein the internal clocking signal is associated with timing of operations performed by the plurality of memory dice.

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