公开(公告)号：US20170286123A1

公开(公告)日：2017-10-05

申请号：US15624956

申请日：2017-06-16

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Po-Wen HUANG ,  Kei-Way CHANG ,  Shih-Ta CHU ,  Jun-Jie WU ,  Chen-Nan HSIAO

IPC: G06F9/44 ,  G06F9/445

CPC classification number: G06F9/4403 ,  G06F8/65 ,  G06F8/654 ,  G06F9/44505

Abstract: A system includes a programmable non-volatile memory, a switch, a control chipset, and a basic input/output (BIOS) module. The switch has a first terminal coupled to the programmable non-volatile memory, and a second terminal coupled to the control chipset. The control chipset is configured to store a SKU parameter set in the programmable non-volatile memory according to a predetermined memory allocation. The BIOS module is coupled to the control chipset, and is configured to load and update the SKU parameter set according to the predetermined memory configuration during a booting operation of the motherboard.

公开(公告)号：US20200097299A1

公开(公告)日：2020-03-26

申请号：US16573864

申请日：2019-09-17

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Po-Wen HUANG ,  Chen-Nan HSIAO ,  Xu ZHANG ,  Wei-Lung SHEN

IPC: G06F9/4401 ,  G06F9/445

Abstract: A synchronization method, which is capable of data synchronization in both directions between a storage medium and a storage unit, includes steps of: determining whether first parameter data of the storage medium is identical to default parameter data stored in the storage medium; determining whether a value of a flag stored in the storage unit is equal to a first logical value; and performing data synchronization between the storage unit and the storage medium based on at least one of the two determinations.

公开(公告)号：US20190286527A1

公开(公告)日：2019-09-19

申请号：US16244639

申请日：2019-01-10

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Wei-Lung SHEN ,  Chen-Nan HSIAO ,  Chih-Cheng WANG ,  Chung-Huang LIU

IPC: G06F11/14 ,  G06F3/06

Abstract: A computer device, a server device, and a method for controlling a hybrid memory unit thereof are provided. The control method includes: executing, by a processing unit, an operating system (OS) in a working mode of the computer device; triggering, by a soft off control signal or a soft reset control signal when the processing unit executes the OS, the processing unit to enter an interrupt processing mode; executing, by the processing unit, basic input/output system (BIOS) program code in the interrupt processing mode; and controlling, by the processing unit by using the BIOS program code, to store data from a volatile memory into a non-volatile memory corresponding to the volatile memory.

公开(公告)号：US20200073773A1

公开(公告)日：2020-03-05

申请号：US16551947

申请日：2019-08-27

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Chung-Huang LIU ,  Chen-Nan HSIAO

IPC: G06F11/22 ,  G06F11/14 ,  G06F11/32 ,  G06F9/4401

Abstract: A method for displaying a basic input-output system (BIOS) message during a power-on self-test (POST) of a computer system includes: after the computer system is connected to a power source, performing, by a baseboard management controller (BMC), an initialization procedure on a display unit so as to control the display unit; executing, by a processor, a BIOS stored in a memory component so as to generate the BIOS message; transmitting, by the processor, the BIOS message to the BMC; and transmitting, by the BMC, the BIOS message to the display unit.

公开(公告)号：US20190146804A1

公开(公告)日：2019-05-16

申请号：US16191509

申请日：2018-11-15

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Po-Wen HUANG ,  Le XING ,  Bichao WANG ,  Cheng-Chieh YEH ,  Jie ZHANG ,  Chen-Nan HSIAO

IPC: G06F9/4401 ,  G06F21/64 ,  G06F3/06

Abstract: A method for synchronization of system management data includes steps of generating a request for system management data in response to execution of a system booting program, transmitting the request to a baseboard management controller so as to enable the baseboard management controller to transmit the system management data stored in a second storage unit to a processor; receiving the system management data from the baseboard management controller, and determining whether the system management data is complete; and when it is determined that the system management data is complete, storing at least one of the sequential packets of the system management data in a first storage unit, and proceeding with execution of the system booting program.

公开(公告)号：US20170220355A1

公开(公告)日：2017-08-03

申请号：US15013832

申请日：2016-02-02

Applicant: MITAC COMPUTING TECHNOLOGY CORPORATION

Inventor： Bo-Wen HUANG ,  Kei-Way CHANG ,  Shih-Ta CHU ,  Jun-Jie WU ,  Chen-Nan HSIAO

IPC: G06F9/44 ,  G06F9/445

CPC classification number: G06F9/4403 ,  G06F1/24 ,  G06F8/65 ,  G06F8/654 ,  G06F9/44505

Abstract: A system includes a programmable non-volatile memory, a switch, a control chipset, and a basic input/output (BIOS) module. The switch has a first terminal coupled to the programmable non-volatile memory, and a second terminal coupled to the control chipset. The control chipset is configured to store a SKU parameter set in the programmable non-volatile memory according to a predetermined memory allocation. The BIOS module is coupled to the control chipset, and is configured to load and update the SKU parameter set according to the predetermined memory configuration during a booting operation of the motherboard.