公开(公告)号：US08780664B2

公开(公告)日：2014-07-15

申请号：US13912650

申请日：2013-06-07

Applicant: Mosaid Technologies Incorporated

Inventor： Byoung Jin Choi

IPC: G11C7/00

CPC classification number: G11C7/12 ,  G11C7/06 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2211/4065

Abstract: A semiconductor memory device, including: a memory cell connected to a first bitline and associated with a second bitline; a sense amplifier, including a first input/output node and a second input/output node; and an isolator connected to the bitlines and to the input/output nodes, the isolator being configured to carry out bitline isolation during a refresh operation of the memory cell, where the bitline isolation includes electrically disconnecting the first bitline from the first input/output node and electrically disconnecting the second bitline from the second input/output node, followed by: electrically re-connecting the first bitline to the first input/output node while the second bitline remains electrically disconnected from the second input/output node.

Abstract translation: 一种半导体存储器件，包括：连接到第一位线并与第二位线相关联的存储器单元; 读出放大器，包括第一输入/输出节点和第二输入/输出节点; 以及连接到所述位线和所述输入/输出节点的隔离器，所述隔离器被配置为在所述存储器单元的刷新操作期间执行位线隔离，其中所述位线隔离包括将所述第一位线与所述第一输入/输出节点电断开 并且将所述第二位线与所述第二输入/输出节点电断开，其后是：将所述第一位线电连接到所述第一输入/输出节点，同时所述第二位线与所述第二输入/输出节点电连接断开。

公开(公告)号：US08824231B2

公开(公告)日：2014-09-02

申请号：US13644528

申请日：2012-10-04

Applicant: MOSAID Technologies Incorporated

Inventor： Byoung Jin Choi

IPC: G11C7/00

CPC classification number: G11C7/12 ,  G11C7/02 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002

Abstract: A dynamic random access memory device is described. A first array has a first plurality of bitlines, each coupled to a column of memory cells. A second has a second plurality of bitlines, each coupled to a column of memory cells. Sense amplifiers are selectively connectable in an open bitline configuration to at least one bitline of the first plurality of bitlines and at least one complementary bitline of the second plurality of bitlines. A voltage supply having a voltage VBL corresponding to a bitline precharge voltage is selectively connectable to each bitline. Logic selectively connects each bitline and the complementary bitline to one of a sense amplifier and the voltage supply during a read operation. Each bitline connected to the sense amplifier is adjacent to a bitline concurrently connected to the voltage supply. A method is also described.

Abstract translation: 描述了动态随机存取存储器件。 第一阵列具有第一多个位线，每个位线耦合到一列存储器单元。 第二个具有第二多个位线，每个位线耦合到一列存储器单元。 感测放大器可以以开放位线配置可选地连接到第一多个位线的至少一个位线和第二多个位线的至少一个互补位线。 具有对应于位线预充电电压的电压VBL的电压源可选择性地连接到每个位线。 在读操作期间，逻辑将每个位线和互补位线选择性地连接到读出放大器之一和电压源。 连接到读出放大器的每个位线与同时连接到电压源的位线相邻。 还描述了一种方法。