公开(公告)号：US20140089575A1

公开(公告)日：2014-03-27

申请号：US14089242

申请日：2013-11-25

Applicant: MOSAID Technologies Incorporated

Inventor： Ian Mes

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract translation: 异步流水线SDRAM具有由异步信号控制的单独流水线级。 不是使用时钟信号在每个阶段同步数据，而是使用异步信号来锁存每个阶段的数据。 异步控制信号在芯片内产生，并针对不同的延迟级进行了优化。 更长的延迟阶段需要更大的延迟元件，而较短的等待时间状态需要更短的延迟元件。 在从芯片读出之前，数据与读取数据路径末端的时钟同步。 由于数据已经在每个流水线阶段被锁存，所以它比在传统的波浪管线架构中看到的偏差更小。 此外，由于这些阶段与系统时钟无关，只要构建重新同步输出以支持读取数据路径，就可以以任何CAS延迟运行。