公开(公告)号：US10089189B2

公开(公告)日：2018-10-02

申请号：US15130498

申请日：2016-04-15

Applicant: MOTOROLA SOLUTIONS, INC.

Inventor： Harish Natarahjan ,  Graeme Peter Johnson ,  Daniel J. McDonald

IPC: G06F11/14 ,  H04W76/15 ,  H04L1/00 ,  H04W76/02

Abstract: Devices and methods for receiving a data file in a communication system. In one embodiment, the wireless communication device includes a transceiver, a memory, and an electronic processor. The transceiver is configured to send and receive data over a wireless communication network. The electronic processor is electrically coupled to the transceiver and the memory and configured to receive, with the transceiver, a first seed, a sequence of blocks, and a subsequent seed, cause the memory to save the sequence of blocks in the memory, and determine whether the subsequent seed is aligned with the first seed. When the subsequent seed is not aligned with the first seed, the electronic processor is configured to cause the memory to delete the sequence of blocks. When the subsequent seed is aligned with the first seed, the electronic processor is configured to cause the memory to maintain the sequence of blocks.

公开(公告)号：US20170300389A1

公开(公告)日：2017-10-19

申请号：US15130498

申请日：2016-04-15

Applicant: MOTOROLA SOLUTIONS, INC.

Inventor： Harish Natarahjan ,  Graeme Peter Johnson ,  Daniel J. McDonald

IPC: G06F11/14 ,  H04L1/00 ,  H04W76/02

CPC classification number: G06F11/1464 ,  G06F2201/84 ,  H04L1/0045 ,  H04L1/0048 ,  H04L1/0056 ,  H04L1/0075 ,  H04W76/15

Abstract: Devices and methods for receiving a data file in a communication system. In one embodiment, the wireless communication device includes a transceiver, a memory, and an electronic processor. The transceiver is configured to send and receive data over a wireless communication network. The electronic processor is electrically coupled to the transceiver and the memory and configured to receive, with the transceiver, a first seed, a sequence of blocks, and a subsequent seed, cause the memory to save the sequence of blocks in the memory, and determine whether the subsequent seed is aligned with the first seed. When the subsequent seed is not aligned with the first seed, the electronic processor is configured to cause the memory to delete the sequence of blocks. When the subsequent seed is aligned with the first seed, the electronic processor is configured to cause the memory to maintain the sequence of blocks.

公开(公告)号：US09615207B1

公开(公告)日：2017-04-04

申请号：US14963963

申请日：2015-12-09

Applicant: MOTOROLA SOLUTIONS, INC

Inventor： David E. Klein ,  Graeme Peter Johnson

IPC: H04W4/02 ,  H04W4/22 ,  H04W4/08 ,  H04W8/24

CPC classification number: H04W4/022 ,  H04W4/02 ,  H04W4/021 ,  H04W4/08 ,  H04W4/90 ,  H04W8/245

Abstract: A method and apparatus for changing geofence-based operating parameters is provided herein. During operation, all members within a first geofence will have their radio parameters change to those used within a second geofence when a member of the first geofence crosses into the second geofence. Therefore, even though a particular member of the first geofence may not have crossed over the second geofence, the particular member will still have their radio parameters changed to those in use within the second geofence if a member of the first geofence has crossed the second geofence.

公开(公告)号：US09614561B2

公开(公告)日：2017-04-04

申请号：US14068225

申请日：2013-10-31

Applicant: MOTOROLA SOLUTIONS, INC

Inventor： Peter J. Bartels ,  Javier Alfaro ,  Stanko Jelavic ,  Graeme Peter Johnson

IPC: H04B1/12 ,  H04W52/02 ,  H04B1/10 ,  H04B15/00

CPC classification number: H04B1/12 ,  H04B1/10 ,  H04B15/00 ,  H04W52/0209 ,  H04W52/0238 ,  Y02D70/166 ,  Y02D70/40

Abstract: A method and circuit for mitigating RFI in an electronic device that occurs while the device is in a low power mode utilizes one or more antenna elements in the device to receive RF energy. When the RF energy is sufficiently high that it could affect signal states in the device while in the low power mode, the device transitions from the low power mode to an active mode and begins an RFI mitigation process to ensure signal states and other circuit operations in the device are not changed by the RFI.