公开(公告)号：US10263813B1

公开(公告)日：2019-04-16

申请号：US15988110

申请日：2018-05-24

Applicant: MStar Semiconductor, Inc.

Inventor： Chia-Chun Hung ,  Ting-Nan Cho ,  Kai-Wen Cheng ,  Tai-Lai Tung

IPC: H04L25/03 ,  H04L27/00

Abstract: A signal receiving apparatus includes a phase recovery look, a phase estimation circuit, a phase noise detection circuit, and a bandwidth setting circuit. The phase recovery loop performs a phase recovery process on an input signal according to a bandwidth setting. The phase estimation circuit generates an estimated phase associated with the input signal. The phase noise detection circuit determines a phase noise amount according to the estimated phase. The bandwidth setting circuit calculates an average and a variance of the phase noise amounts, and adjusts the bandwidth setting of the phase recovery loop according to the average and the variance.

公开(公告)号：US10224971B1

公开(公告)日：2019-03-05

申请号：US15909116

申请日：2018-03-01

Applicant: MStar Semiconductor, Inc.

Inventor： Ting-Nan Cho ,  Kai-Wen Cheng ,  Tai-Lai Tung

IPC: H04B1/12 ,  H04B1/10 ,  H04L25/02

Abstract: A symbol rate estimating device includes: a power spectrum density (PSD) estimating unit, estimating a PSD of an input signal; an index searching unit, searching for a cut-off frequency index in the PSD; an adjacent channel interference (ACI) detecting unit, detecting whether the input signal has ACI to generate a detection signal; a threshold adjusting unit, generating an adjusted index number threshold according to the detection signal; an index output unit, outputting the cut-off frequency index according to the adjusted index number threshold; and a symbol calculating unit, calculating a symbol rate of the input signal according to the cut-off frequency index.

公开(公告)号：US10230551B2

公开(公告)日：2019-03-12

申请号：US15890466

申请日：2018-02-07

Applicant: MStar Semiconductor, Inc.

Inventor： Ting-Nan Cho ,  Chia-Wei Chen ,  Kai-Wen Cheng ,  Tai-Lai Tung

IPC: H04L25/03 ,  H04L7/00 ,  H04B7/185

Abstract: A signal processing device for a receiver includes: a descrambler, descrambling an input signal to generate a descrambled signal; a phase recovery circuit, performing phase recovery according to the descrambled signal to generate a phase recovered signal; an equalization module, performing equalization according to the phase recovered signal to generate an equalized signal; and a decoder, decoding the equalized signal to obtain data included in the input signal.

公开(公告)号：US10135603B2

公开(公告)日：2018-11-20

申请号：US15889547

申请日：2018-02-06

Applicant: MStar Semiconductor, Inc.

Inventor： Ting-Nan Cho ,  Yi-Ying Liao ,  Ko-Yin Lai ,  Tai-Lai Tung

IPC: H04L7/00 ,  H04L27/00 ,  H04B1/10 ,  H04L25/02

Abstract: A carrier frequency offset (CFO) tracking circuit includes: a CFO estimation circuit, generating an estimated CFO signal; a loop filter, coupled to the CFO estimation circuit, performing a loop filter operation on the estimated CFO signal according to an initial value to generate a loop filtered result; and an averaging circuit, coupled to the CFO estimation circuit and the loop filter, performing an average operation on the estimated CFO signal to generate the initial value as an average of the estimated CFO signal.

公开(公告)号：US10075285B2

公开(公告)日：2018-09-11

申请号：US15610743

申请日：2017-06-01

Applicant: MStar Semiconductor, Inc.

Inventor： Ting-Nan Cho ,  Kai-Wen Cheng ,  Tai-Lai Tung

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04L7/0331 ,  H03L7/0807 ,  H03L7/093 ,  H03L7/10 ,  H04L7/0016 ,  H04L27/00 ,  H04L2027/0053

Abstract: A bandwidth adjusting method for a phase-locked loop (PLL) unit of a phase recovery module includes: adjusting an operating bandwidth of the PLL unit to a first bandwidth; measuring multiple first phase errors between a compensated input signal, which is generated according to an input signal and a phase compensating signal that the PLL unit generates, and a reference clock signal, and obtaining a first statistical value of the first phase errors; adjusting the operating bandwidth of the PLL unit to a second bandwidth; measuring multiple second phase differences between the compensated input signal and the reference clock signal, and obtaining a second statistical value of the second phase differences; and adjusting the operating bandwidth according to the first statistical value and the second statistical value. The first bandwidth and the second bandwidth are obtained by interpolating an upper bandwidth limit and a lower bandwidth limit.

公开(公告)号：US20180248678A1

公开(公告)日：2018-08-30

申请号：US15889547

申请日：2018-02-06

Applicant: MStar Semiconductor, Inc.

Inventor： Ting-Nan Cho ,  Yi-Ying Liao ,  Ko-Yin Lai ,  Tai-Lai Tung

IPC: H04L7/00 ,  H04L27/00 ,  H04L25/02 ,  H04B1/10

CPC classification number: H04L7/0087 ,  H04B1/1027 ,  H04L25/024 ,  H04L27/0014 ,  H04L2027/003 ,  H04L2027/0069

Abstract: A carrier frequency offset (CFO) tracking circuit includes: a CFO estimation circuit, generating an estimated CFO signal; a loop filter, coupled to the CFO estimation circuit, performing a loop filter operation on the estimated CFO signal according to an initial value to generate a loop filtered result; and an averaging circuit, coupled to the CFO estimation circuit and the loop filter, performing an average operation on the estimated CFO signal to generate the initial value as an average of the estimated CFO signal.