公开(公告)号：US10598776B2

公开(公告)日：2020-03-24

申请号：US15639049

申请日：2017-06-30

申请人： MStar Semiconductor, Inc.

发明人： Ming-Han Weng ,  Wei-Yung Wang ,  Chih-Hung Lin ,  Jyun Yang Shih ,  Chun-Chia Chen

IPC分类号： H03K5/135 ,  H03K5/151 ,  H03L7/08 ,  H03L7/091 ,  G01S13/28 ,  H04N7/18 ,  G11C7/22

摘要： An electronic device includes a clock generating circuit, a receiving circuit and a training circuit. The clock generating circuit generates a sampling clock signal, a phase-early sampling clock signal and a phase-late sampling clock signal. The receiving circuit samples received data according to the sampling clock signal, the phase-early sampling clock signal and the phase-late sampling clock signal to generate a sample result. The training circuit controls the clock generating circuit to generate the sampling clock signal and the corresponding phase-early sampling clock signal and phase-late sampling clock signal that have different phases in a plurality of different time intervals, respectively, to cause the receiving circuit to generate a plurality of sample results. The training circuit further determines a sampling phase of the sampling clock signal according to the sample results.