公开(公告)号：US20160307836A1

公开(公告)日：2016-10-20

申请号：US14687015

申请日：2015-04-15

Applicant: Macronix International Co., Ltd.

Inventor： Ya Jung TSai ,  Lan Ting Huang ,  Kuo NaiPing ,  Chun-Lien Su

IPC: H01L23/528 ,  H01L29/78 ,  H01L29/08 ,  H01L27/105

CPC classification number: H01L29/0847 ,  G11C7/18 ,  H01L27/0207

Abstract: A semiconductor memory device is provided including a plurality of diffusion region pairs comprising first and second diffusion regions, wherein each of the diffusion regions comprise source and drain regions of a bit line transistor pair comprising a first bit line transistor and a second bit line transistor and a plurality of bit line transistor gate pairs in contact with the respective diffusion region pairs, wherein the first bit line transistor gate of the bit line transistor gate pairs comprises a gate portion of a first bit line transistor of the first diffusion region and the first bit lite transistor of the second diffusion region, wherein a second bit line transistor gate of the bit line transistor gate pairs comprises a gate portion of the second bit line transistor of the first diffusion region and the second bit line transistor of the second diffusion layer.

Abstract translation: 提供一种半导体存储器件，其包括多个扩散区域对，其包括第一和第二扩散区域，其中每个扩散区域包括包含第一位线晶体管和第二位线晶体管的位线晶体管对的源区和漏区， 与相应的扩散区域对接触的多个位线晶体管栅极对，其中位线晶体管栅极对的第一位线晶体管栅极包括第一扩散区域的第一位线晶体管的栅极部分和第一位 位线晶体管栅极对的第二位线晶体管栅极包括第一扩散区域的第二位线晶体管的栅极部分和第二扩散层的第二位线晶体管。