公开(公告)号：US20240153564A1

公开(公告)日：2024-05-09

申请号：US17981919

申请日：2022-11-07

Applicant: Macronix International Co., Ltd.

Inventor： Wei-Han Chen ,  Chun-Hsiung Hung

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/26

Abstract: Systems, methods, circuits, and apparatus for managing multi-block operations in memory devices are provided. In one aspect, a memory device includes a memory cell array including at least two blocks, a bit line coupled to a string of memory cells in each of the at least two blocks respectively, a common source line (CSL) coupled to strings coupled to the bit line in the at least two blocks, and a circuitry configured to perform a multi-block operation in the memory cell array by at least one of: forming a first current path from the bit line through the strings to the CSL coupled to a ground to discharge a capacitor associated with the bit line that is pre-charged, or forming a second current path from the CSL coupled to a supply voltage through the strings to the bit line to charge the capacitor that is pre-discharged.