公开(公告)号：US20190206498A1

公开(公告)日：2019-07-04

申请号：US15857940

申请日：2017-12-29

Applicant: Macronix International Co., Ltd.

Inventor： Yiching Liu ,  Chun-Hsiung Hung

IPC: G11C16/22 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/02 ,  G11C16/04

CPC classification number: G11C16/22 ,  G11C16/0483 ,  G11C16/08 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/0255 ,  H01L27/11526 ,  H01L27/11573

Abstract: Systems, methods, circuits, and apparatus including computer-readable mediums for protecting memory cells from in-process charging effects for a memory system, e.g., NAND flash memory. The methods include: forming a first connection to connect a first node of a diode to a memory cell line coupled with one or more memory cells to be fabricated and a second connection to connect a second node of the diode to a control circuit, such that, during fabricating the memory, in-process charges accumulated on the memory cells are discharged to a ground via a conductive path formed by a first voltage caused by the in-process charges forward biasing the diode and then enabling the control circuit to conduct a current to the ground, and after fabricating the memory and during operating the memory, turning off the conductive path by reverse biasing the diode with a second voltage applied on the control circuit.

公开(公告)号：US10916310B2

公开(公告)日：2021-02-09

申请号：US16408526

申请日：2019-05-10

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Chun Liu ,  Yiching Liu

IPC: G11C16/04 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34

Abstract: Methods, systems and apparatus including computer-readable mediums for partially erasing blocks in a memory system to increase reliability are provided. In one aspect, a memory system includes a memory having a plurality of blocks and a memory controller coupled to the memory. The memory controller is configured to: execute a first erase operation on a particular block in the memory, the particular block including multiple sub-blocks each having respective memory cells, one or more memory cells in the particular block being in one or more programmed states before the first erase operation, then execute a second erase operation on a first sub-block of the particular block such that first respective memory cells of the first sub-block are in an erased state after the second erase operation. The memory controller can be configured to not execute the second erase operation on the one or more other sub-blocks of the particular block.

公开(公告)号：US10325663B1

公开(公告)日：2019-06-18

申请号：US15857940

申请日：2017-12-29

Applicant: Macronix International Co., Ltd.

Inventor： Yiching Liu ,  Chun-Hsiung Hung

IPC: G11C16/22 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/02 ,  G11C16/04 ,  H01L27/11526 ,  G11C16/08

CPC classification number: G11C16/22 ,  G11C16/0483 ,  G11C16/08 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/0255 ,  H01L27/11526 ,  H01L27/11573

Abstract: Systems, methods, circuits, and apparatus including computer-readable mediums for protecting memory cells from in-process charging effects for a memory system, e.g., NAND flash memory. The methods include: forming a first connection to connect a first node of a diode to a memory cell line coupled with one or more memory cells to be fabricated and a second connection to connect a second node of the diode to a control circuit, such that, during fabricating the memory, in-process charges accumulated on the memory cells are discharged to a ground via a conductive path formed by a first voltage caused by the in-process charges forward biasing the diode and then enabling the control circuit to conduct a current to the ground, and after fabricating the memory and during operating the memory, turning off the conductive path by reverse biasing the diode with a second voltage applied on the control circuit.