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1.发明申请公开(公告)号：US20110025372A1
公开(公告)日：2011-02-03
申请号：US12511207
申请日：2009-07-29
IPC分类号： H03K19/003 , H03K3/289 , G06F17/50
CPC分类号： G11C5/005 , G11C7/02 , H03K3/0375 , H03K3/356121 , H03K17/693
摘要： The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.
摘要翻译： 不同的有利实施例提供了包括多个锁存器和多个滤波器的集成电路。 锁存器数量中的每个锁存器具有多个输入和多个存储节点。 多个存储节点包括形成多个可压缩电路节点对的多对电路节点。 多个输入的每个输入连接到多个存储节点中的对应的存储节点。 多个滤波器中的每个滤波器具有输入和多个输出。 多个输出中的每一个连接到锁存器数量的锁存器的多个输入的相应输入。 滤波器数量中的每个滤波器位于两个电路节点之间，形成锁存器数量的锁存器的可升高电路节点对以增加关键节点间隔。
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2.发明授权Method and apparatus for reducing radiation and cross-talk induced data errors 有权减少辐射和串扰引起的数据错误的方法和装置公开(公告)号：US08054099B2
公开(公告)日：2011-11-08
申请号：US12511207
申请日：2009-07-29
IPC分类号： H03K19/003 , H03K19/00 , G11C11/00
CPC分类号： G11C5/005 , G11C7/02 , H03K3/0375 , H03K3/356121 , H03K17/693
摘要： The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.
摘要翻译： 不同的有利实施例提供了包括多个锁存器和多个滤波器的集成电路。 锁存器数量中的每个锁存器具有多个输入和多个存储节点。 多个存储节点包括形成多个可压缩电路节点对的多对电路节点。 多个输入的每个输入连接到多个存储节点中的对应的存储节点。 多个滤波器中的每个滤波器具有输入和多个输出。 多个输出中的每一个连接到锁存器数量的锁存器的多个输入的相应输入端。 滤波器数量中的每个滤波器位于两个电路节点之间，形成锁存器数量的锁存器的可升高电路节点对以增加关键节点间隔。
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3.发明授权Method and apparatus for reducing radiation and cross-talk induced data errors 有权减少辐射和串扰引起的数据错误的方法和装置公开(公告)号：US08207753B2
公开(公告)日：2012-06-26
申请号：US13015331
申请日：2011-01-27
IPC分类号： H03K19/003 , H03K19/00
CPC分类号： G11C5/005 , G11C7/02 , H03K3/0375 , H03K3/356121 , H03K17/693
摘要： The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.
摘要翻译： 不同的有利实施例提供了包括多个锁存器和多个滤波器的集成电路。 锁存器数量中的每个锁存器具有多个输入和多个存储节点。 多个存储节点包括形成多个可压缩电路节点对的多对电路节点。 多个输入的每个输入连接到多个存储节点中的对应的存储节点。 多个滤波器中的每个滤波器具有输入和多个输出。 多个输出中的每一个连接到锁存器数量的锁存器的多个输入的相应输入端。 滤波器数量中的每个滤波器位于两个电路节点之间，形成锁存器数量的锁存器的可升高电路节点对以增加关键节点间隔。
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公开(公告)号：US20110309856A1
公开(公告)日：2011-12-22
申请号：US13015331
申请日：2011-01-27
IPC分类号： H03K19/003 , G06F17/50
CPC分类号： G11C5/005 , G11C7/02 , H03K3/0375 , H03K3/356121 , H03K17/693
摘要： The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.
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