公开(公告)号：US07428274B2

公开(公告)日：2008-09-23

申请号：US10153000

申请日：2002-05-22

申请人： Marc Joisson ,  Luc Garcia ,  Sebastien Leveque

发明人： Marc Joisson ,  Luc Garcia ,  Sebastien Leveque

IPC分类号： H03D3/00 ,  H04L27/14

CPC分类号： H04L27/1563

摘要： A receiver of a frequency-modulated signal representing a digital signal includes a down conversion unit or frequency translation unit to lower the frequency of the frequency-modulated signal and a digital demodulator to regenerate the digital signal from the lowered-frequency signal. The receiver furthermore includes a counter circuit to determine the number of periods of a reference signal from the frequency translation unit during a period of the lowered-frequency signal. The digital demodulator includes a computer unit to compute the period of the lowered-frequency signal from the number of periods of the reference signal.

摘要翻译： 表示数字信号的频率调制信号的接收机包括降频变频单元或频率转换单元，以降低频率调制信号的频率，以及数字解调器，以从低频信号再生数字信号。 接收器还包括一个计数器电路，用于在降频信号的周期期间确定来自频率转换单元的参考信号的周期数。 数字解调器包括计算机单元，用于根据参考信号的周期数来计算降频信号的周期。

公开(公告)号：US07379512B2

公开(公告)日：2008-05-27

申请号：US10103575

申请日：2002-03-21

申请人： Marc Joisson ,  Luc Garcia ,  Marc Gens

发明人： Marc Joisson ,  Luc Garcia ,  Marc Gens

IPC分类号： H03D3/24

CPC分类号： H04L27/1566

摘要： A receiver of a frequency-modulated signal is provided. The receiver includes a frequency-transposition unit for lowering the frequency of the frequency-modulated signal, and a digital demodulator for regenerating a digital signal from the frequency-transposed signal. The frequency-transposition unit includes a local oscillator for generating a local oscillator signal used in lowering the frequency of the frequency-modulated signal. The frequency-transposed signal is sampled in the digital demodulator at the rate of a sampling signal, and the sampling signal is generated by the local oscillator of the frequency-transposition unit. In a preferred embodiment, the local oscillator includes at least one frequency-divider circuit that delivers the sampling signal. Also provided is a method for regenerating a digital signal from a frequency-modulated signal.

摘要翻译： 提供了调频信号的接收机。 接收机包括用于降低频率调制信号的频率的频率转置单元和用于从频率转置信号再生数字信号的数字解调器。 频率转置单元包括本地振荡器，用于产生用于降低频率调制信号的频率的本地振荡器信号。 在数字解调器中以采样信号的速率采样频移信号，采样信号由频移单元的本地振荡器产生。 在优选实施例中，本地振荡器包括传送采样信号的至少一个分频器电路。 还提供了一种从频率调制信号再生数字信号的方法。

公开(公告)号：US07519335B2

公开(公告)日：2009-04-14

申请号：US11247989

申请日：2005-10-11

申请人： Benoit Butaye ,  Luc Garcia

发明人： Benoit Butaye ,  Luc Garcia

IPC分类号： H01Q11/12 ,  H04B1/04

CPC分类号： H03D7/1433 ,  H03D7/1425 ,  H03D7/145 ,  H03D7/1458 ,  H03D7/165

摘要： The present invention includes a mixer circuit integrating a voltage-to-currrent conversion in the same stage. A mixer device 20 of a transmission system comprises a pair of transistors 41 and 42 forming a differential circuit having two differential inputs receiving a carrier VLO, two differential current outputs delivering a differential output current and a common current output whose current is equal to the sum of the differential output currents; a current-to-voltage conversion element 47 coupled to the common current output of the pair of transistors; an amplifier 30 having a positive input receiving the modulating signal, a negative feedback input coupled to the current-to-voltage conversion element, and an output coupled to each of the differential inputs of the pair of transistors.

摘要翻译： 本发明包括在同一级集成电压 - 电流转换的混频电路。 传输系统的混频器装置20包括一对晶体管41和42，其形成具有接收载波VLO的两个差分输入的差分电路，传递差分输出电流的两个差分电流输出和电流等于总和的公共电流输出 的差分输出电流; 耦合到该对晶体管的公共电流输出的电流 - 电压转换元件47; 具有接收调制信号的正输入的放大器30，耦合到电流 - 电压转换元件的负反馈输入和耦合到该对晶体管的每个差分输入的输出。

公开(公告)号：US06806748B2

公开(公告)日：2004-10-19

申请号：US10101561

申请日：2002-03-19

申请人： Luc Garcia

发明人： Luc Garcia

IPC分类号： H03B1900

CPC分类号： H03D3/007

摘要： A sinusoidal signal multiplier circuit produces an output sinusoidal signal substantially without any DC component. This sinusoidal signal multiplier circuit includes a first multiplication cell receiving a first sinusoidal signal at a first input and a second sinusoidal signal at a second input. The first multiplication cell delivers a first output signal. The sinusoidal signal multiplier circuit also includes a second multiplication cell, identical to the first multiplication cell, that receives the second sinusoidal signal at its first input and the first sinusoidal signal at its second input, and delivers a second output signal. The sinusoidal signal multiplier circuit also includes an adder circuit to add the first output signal and the second output signal to provide from the sinusoidal signal multiplier circuit an output signal substantially without any DC component.

摘要翻译： 正弦信号乘法器电路基本上没有任何DC分量产生输出正弦信号。 该正弦信号乘法器电路包括在第一输入处接收第一正弦信号的第一乘法单元和第二输入端的第二正弦信号。 第一乘法单元传送第一输出信号。 正弦信号乘法器电路还包括与第一乘法单元相同的第二乘法单元，其在其第一输入处接收第二正弦信号，并在其第二输入端接收第一正弦信号，并传送第二输出信号。 正弦信号乘法器电路还包括加法器电路，用于将第一输出信号和第二输出信号相加，以从正弦信号乘法器电路提供基本上没有任何DC分量的输出信号。

公开(公告)号：US5954660A

公开(公告)日：1999-09-21

申请号：US3765

申请日：1998-01-07

申请人： Thierry Legay ,  Pascal Pons ,  Luc Garcia

发明人： Thierry Legay ,  Pascal Pons ,  Luc Garcia

IPC分类号： A61B5/0402 ,  A61B5/0452 ,  A61N1/36 ,  A61N1/37 ,  H03H11/04

CPC分类号： A61N1/3704 ,  Y10S128/902

摘要： A device for filtering cardiac activity signals which receives input signals coming from collected physiological data, and delivers at an output, for processing data, signals spreading, in the frequency domain, over a widened spectral band. A first high-pass filter is used to reduce the extension of the spectral band of the signal received at the input. A compensation stage having a frequency characteristic (32) that is inverted as compared to that of the first high-pass filter is provided. The cut-off frequency (f1) of the first high-pass filter is greater than the low cut-off frequency (fo) of the spectral analysis band. Optionally, a second high-pass filter is provided, whose characteristic (38) presents a cut-off frequency corresponding to the low frequency (fo) of the spectral band. The high frequency of the spectral band may be similarly modified.

摘要翻译： 一种用于过滤心脏活动信号的装置，其接收来自收集的生理数据的输入信号，并且在输出处传送用于处理数据的信号，在频域中扩展在扩展的频谱带上的信号。 第一个高通滤波器用于减少在输入端接收的信号的频谱带的扩展。 提供了具有与第一高通滤波器相反的频率特性（32）的补偿级。 第一高通滤波器的截止频率（f1）大于频谱分析频带的低截止频率（fo）。 可选地，提供第二高通滤波器，其特征（38）呈现对应于频谱带的低频（fo）的截止频率。 可以类似地修改频谱带的高频率。

公开(公告)号：US20130196611A1

公开(公告)日：2013-08-01

申请号：US13786637

申请日：2013-03-06

申请人： Frederic Duez ,  Luc Garcia ,  Benoit Butaye ,  Jerome Lajoinie ,  Thierry Lapergue ,  Mathilde Sie

发明人： Frederic Duez ,  Luc Garcia ,  Benoit Butaye ,  Jerome Lajoinie ,  Thierry Lapergue ,  Mathilde Sie

IPC分类号： H03D7/14

CPC分类号： H03D7/1466 ,  H03D7/165

摘要： A frequency conversion device for transforming a frequency of an input signal, the device comprising: a signal generator for providing a plurality N of first signals at a first frequency, where N≧1, from an input signal having an in-phase component I and a quadrature signal component Q; an oscillator for generating N parallel oscillation signals, wherein the N oscillation signals are stepped in phase with respect to one another; a mixer comprising N mixing components, each mixing component being coupled to receive a respective one of the plurality of first signals and coupled to receive a respective oscillation signal for mixing the respective first signal with the corresponding oscillation signal to provide an output signal; and a common amplifier for receiving the N output signals from the N mixing components in N sequential phases for transmission.

摘要翻译： 一种用于变换输入信号的频率的变频装置，所述装置包括：信号发生器，用于从具有同相分量I的输入信号中提供第一频率的多个N个第一信号，其中N≥1 和正交信号分量Q; 用于产生N个并联振荡信号的振荡器，其中所述N个振荡信号相对于彼此同步地阶梯状; 混合器，其包括N个混合分量，每个混合分量被耦合以接收所述多个第一信号中的相应一个，并且被耦合以接收相应的振荡信号，用于将相应的第一信号与相应的振荡信号混合以提供输出信号; 以及用于从N个混合分量中以N个连续相位接收N个输出信号以用于传输的公共放大器。

公开(公告)号：US20060071707A1

公开(公告)日：2006-04-06

申请号：US11244773

申请日：2005-10-06

申请人： Fabrice Belveze ,  Luc Garcia

发明人： Fabrice Belveze ,  Luc Garcia

IPC分类号： H03K5/00

CPC分类号： H03H15/00

摘要： A filter intended to receive a discrete time signal at a sampling dock frequency, comprising a determined number, greater than 2, of filtering units, each filtering unit comprising head capacitors in a number equal to the determined number, assembled in parallel between an input terminal and the terminal of an integration capacitor; and means for connecting, in successive dock cycles in a number equal to the determined number, successively each head capacitor to the input terminal, and for then simultaneously connecting the head capacitors to the integration capacitor, and in which the successive dock cycles during which the head capacitors of a filtering unit are connected to the input terminal are offset by one dock cycle from one filtering unit to the next one.

摘要翻译： 一种用于以采样驻留频率接收离散时间信号的滤波器，包括大于2的滤波单元的确定数量，每个滤波单元包括数量等于所确定数量的头电容器，并联在输入端子 和集成电容器的端子; 以及用于在相等于所确定的数量的连续停靠周期中连续地将每个头电容器连接到输入端子并且然后将头电容器同时连接到积分电容器的装置，并且其中连续对接周期 连接到输入端子的滤波单元的头电容器被从一个滤波单元到下一个滤波单元的一个停靠周期偏移。

公开(公告)号：US07539721B2

公开(公告)日：2009-05-26

申请号：US11244773

申请日：2005-10-06

申请人： Fabrice Belveze ,  Luc Garcia

发明人： Fabrice Belveze ,  Luc Garcia

IPC分类号： G06G7/02

CPC分类号： H03H15/00

摘要： A filter intended to receive a discrete time signal at a sampling clock frequency, comprising a determined number, greater than 2, of filtering units, each filtering unit comprising head capacitors in a number equal to the determined number, assembled in parallel between an input terminal and the terminal of an integration capacitor; and means for connecting, in successive clock cycles in a number equal to the determined number, successively each head capacitor to the input terminal, and for then simultaneously connecting the head capacitors to the integration capacitor, and in which the successive clock cycles during which the head capacitors of a filtering unit are connected to the input terminal are offset by one clock cycle from one filtering unit to the next one.

摘要翻译： 旨在以采样时钟频率接收离散时间信号的滤波器，包括大于2的滤波单元的确定数量，每个滤波单元包括数量等于所确定数量的头电容器，并联在输入端子 和集成电容器的端子; 以及用于在等于确定数量的连续时钟周期中连续地将每个头电容器连接到输入端子并且然后同时将头电容器连接到积分电容器的装置，并且其中连续的时钟周期 连接到输入端子的滤波单元的头电容器从一个滤波单元偏移到一个时钟周期。

公开(公告)号：US08275823B2

公开(公告)日：2012-09-25

申请号：US12472356

申请日：2009-05-26

申请人： Fabrice Belveze ,  Luc Garcia

发明人： Fabrice Belveze ,  Luc Garcia

IPC分类号： G06G7/02

CPC分类号： H03H15/00

摘要： A filter intended to receive a discrete time signal at a sampling clock frequency, comprising a determined number, greater than 2, of filtering units, each filtering unit comprising head capacitors in a number equal to the determined number, assembled in parallel between an input terminal and the terminal of an integration capacitor, and means for connecting, in successive clock cycles in a number equal to the determined number, successively each head capacitor to the input terminal, and for then simultaneously connecting the head capacitors to the integration capacitor, and in which the successive clock cycles during which the head capacitors of a filtering unit are connected to the input terminal are offset by one clock cycle from one filtering unit to the next one.

摘要翻译： 旨在以采样时钟频率接收离散时间信号的滤波器，包括大于2的滤波单元的确定数量，每个滤波单元包括数量等于所确定数量的头电容器，并联在输入端子 和积分电容器的端子，以及用于在等于确定数量的数量的连续时钟周期中连续地将每个磁头电容器连接到输入端子，并且然后同时将磁头电容器连接到积分电容器的装置，以及在 其中过滤单元的磁头电容器连接到输入端子的连续时钟周期从一个滤波单元偏移到下一个时钟周期。

公开(公告)号：US20090322580A1

公开(公告)日：2009-12-31

申请号：US12472356

申请日：2009-05-26

申请人： Fabrice Belveze ,  Luc Garcia

发明人： Fabrice Belveze ,  Luc Garcia

IPC分类号： H03M1/12

CPC分类号： H03H15/00

摘要： A filter intended to receive a discrete time signal at a sampling dock frequency, comprising a determined number, greater than 2, of filtering units, each filtering unit comprising head capacitors in a number equal to the determined number, assembled in parallel between an input terminal and the terminal of an integration capacitor; and means for connecting, in successive clock cycles in a number equal to the determined number, successively each head capacitor to the input terminal, and for then simultaneously connecting the head capacitors to the integration capacitor, and in which the successive dock cycles during which the head capacitors of a filtering unit are connected to the input terminal are offset by one dock cycle from one filtering unit to the next one.

摘要翻译： 一种用于以采样驻留频率接收离散时间信号的滤波器，包括大于2的滤波单元的确定数量，每个滤波单元包括数量等于所确定数量的头电容器，并联在输入端子 和集成电容器的端子; 以及用于在等于确定数量的连续时钟周期中连续地将每个头电容器连接到输入端子并且然后同时将头电容器连接到积分电容器的装置，并且其中连续的对接周期 连接到输入端子的滤波单元的头电容器被从一个滤波单元到下一个滤波单元的一个停靠周期偏移。