公开(公告)号：US07346860B1

公开(公告)日：2008-03-18

申请号：US10796699

申请日：2004-03-08

申请人： Marcel A. LeBlanc ,  James G. Schleicher

发明人： Marcel A. LeBlanc ,  James G. Schleicher

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： An interface for a programmable logic device having a non-volatile memory where a portion of the non-volatile memory is user accessible is provided. A megafunction provides the electronic circuit designer with interface protocol options for the user accessible portion of the non-volatile memory block. The circuitry associated with the user selected interface is then programmed into the programmable logic device.

摘要翻译： 提供了一种具有非易失性存储器的可编程逻辑器件的接口，其中非易失性存储器的一部分是用户可访问的。 宏功能为电子电路设计者提供用于非易失性存储器块的用户可访问部分的接口协议选项。 然后将与用户选择的接口相关联的电路编程到可编程逻辑器件中。

公开(公告)号：US5949991A

公开(公告)日：1999-09-07

申请号：US940248

申请日：1997-09-30

申请人： Marcel A. LeBlanc

发明人： Marcel A. LeBlanc

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method of analyzing a plurality of signal propagation delays along a plurality of signal interconnection lines within a programmable integrated circuit using a distributed electrical circuit model for the signal interconnection lines which programmably interconnect the electronic circuits forming the cooperative logic functions within the programmable integrated circuit. Load models representing such electronic circuits are incorporated into the circuit model for the signal interconnection lines, and differential nodal equations are generated in accordance with Kirchhoff's Current Law. The differential equations are converted to linear equations in which time is expressed in terms of a finite time interval, or time step. The linear equations are simplified by using substitution techniques for the common variables, thereby producing simplified linear nodal equations which can be collectively represented in a matrix format which includes a square quasi-diagonal coefficient matrix in which all elements more than one element away from the major diagonal thereof have a zero value. Such simplified linear nodal equations can be quickly and easily solved to compute the signal propagation delays along the signal interconnection lines, thereby facilitating any necessary redesign of such signal interconnection lines so as to reduce critical signal propagation delays.

摘要翻译： 使用可编程地将形成可编程集成电路中的协同逻辑功能的电子电路互连的信号互连线的分布式电路模型来分析可编程集成电路内的多个信号互连线的多个信号传输延迟的方法。 代表这种电子电路的负载模型被并入用于信号互连线的电路模型中，并且根据基尔霍夫电流法产生微分节点方程。 微分方程被转换为线性方程，其中时间以有限时间间隔或时间步长表示。 通过使用公共变量的替代技术来简化线性方程，从而产生简化的线性节点方程，其可以以包括正方形对角系数矩阵的矩阵格式共同表示，其中所有元素远离主要 其对角线具有零值。 这种简化的线性节点方程可以快速和容易地求解以计算沿着信号互连线的信号传播延迟，从而有助于这种信号互连线的任何必要的重新设计，以便减少临界信号传播延迟。

公开(公告)号：US07724598B1

公开(公告)日：2010-05-25

申请号：US11737654

申请日：2007-04-19

申请人： Vinson Chan ,  Chong H. Lee ,  Binh Ton ,  Thiagaraja Gopalsamy ,  Marcel A. LeBlanc ,  Neville Carvalho

发明人： Vinson Chan ,  Chong H. Lee ,  Binh Ton ,  Thiagaraja Gopalsamy ,  Marcel A. LeBlanc ,  Neville Carvalho

IPC分类号： G11C7/00

CPC分类号： G06F12/0292 ,  G06F12/0623 ,  G06F2212/1048

摘要： A megafunction block is provided that includes a serial interface enabling a user to specify settings of a configurable block of a programmable logic device. The megafunction block includes a register array having the capability of translating address information into actual addresses for a memory of the configurable block. Thus, as future configurations/standards are developed that a programmable logic device with the megafunction block will interfaces with, the settings for interfacing with the standards may be added to the register array. Consequently, the pin count will not need to increase as the megafunction block is scalable through the register map. Control logic verifies that the translated address is a valid address and the control logic will generate a selection signal based on whether a read or write operation is to be performed.

摘要翻译： 提供了一种宏功能块，其包括使得用户能够指定可编程逻辑器件的可配置块的设置的串行接口。 宏功能块包括具有将地址信息转换成可配置块的存储器的实际地址的能力的寄存器阵列。 因此，随着具有宏功能块的可编程逻辑器件将与之相接的未来配置/标准被开发，用于与标准接口的设置可被添加到寄存器阵列中。 因此，引脚数不需要增加，因为宏功能块可通过寄存器映射进行扩展。 控制逻辑验证翻译的地址是否是有效地址，并且控制逻辑将基于是执行读操作还是写操作来生成选择信号。

公开(公告)号：US07911240B1

公开(公告)日：2011-03-22

申请号：US11750293

申请日：2007-05-17

申请人： Gary Lai ,  Andy L. Lee ,  Ryan Fung ,  Vaughn Betz ,  Marcel A. LeBlanc

发明人： Gary Lai ,  Andy L. Lee ,  Ryan Fung ,  Vaughn Betz ,  Marcel A. LeBlanc

IPC分类号： G06F1/08

CPC分类号： G06F1/10

摘要： Clock switch-over circuits and methods provide clock signals to clock routing networks. According to one embodiment, a multiplexer selects between a first clock signal and a second clock signal in response to a switch select signal received from a control circuit. A storage circuit stores an enable signal in response to an output clock signal of the multiplexer. A logic circuit transmits the output clock signal of the multiplexer to a clock routing network in response to the enable signal from the storage circuit. At least one signal is transmitted from the clock switch-over circuit to the control circuit.

摘要翻译： 时钟切换电路和方法为时钟路由网络提供时钟信号。 根据一个实施例，多路复用器响应于从控制电路接收的开关选择信号在第一时钟信号和第二时钟信号之间进行选择。 存储电路响应于多路复用器的输出时钟信号而存储使能信号。 响应于来自存储电路的使能信号，逻辑电路将多路复用器的输出时钟信号传输到时钟路由网络。 至少一个信号从时钟切换电路发送到控制电路。

公开(公告)号：US5878250A

公开(公告)日：1999-03-02

申请号：US868612

申请日：1997-06-04

申请人： Marcel A. LeBlanc

发明人： Marcel A. LeBlanc

IPC分类号： G11C7/10 ,  G06Z13/36

CPC分类号： G11C7/1078

摘要： Circuitry is provided that allows a register without an asynchronous loading capability to be asynchronously loaded. Logic gates are provided before and after the register. The logic gates are driven by an output signal from a storage circuit such as a latch. When the output signal has one value the logic gates act as non-inverting buffers. When the output signal has another value the logic gates act as inverters. The circuitry allows the normal synchronous operations of the register to be maintained. A hazard coverage circuit can be provided to prevent glitches from appearing at the output during asynchronous operations. The logic gates may be formed from exclusive OR gates implemented in programmable logic on a programmable logic device.

摘要翻译： 提供了允许非异步加载能力的寄存器被异步加载的电路。 在寄存器之前和之后提供逻辑门。 逻辑门由来自诸如锁存器之类的存储电路的输出信号驱动。 当输出信号具有一个值时，逻辑门用作非反相缓冲器。 当输出信号具有另一个值时，逻辑门用作反相器。 电路允许保持寄存器的正常同步操作。 可以提供危险覆盖电路，以防止在异步操作期间在输出端出现毛刺。 逻辑门可以由在可编程逻辑器件上的可编程逻辑中实现的异或门形成。

公开(公告)号：US08219844B1

公开(公告)日：2012-07-10

申请号：US12534788

申请日：2009-08-03

申请人： Marcel A. LeBlanc

发明人： Marcel A. LeBlanc

IPC分类号： G06F1/04

CPC分类号： H03K5/135

摘要： A synchronous clear emulation circuit is provided. The synchronous clear emulation circuit includes a register having an asynchronous clear port. Moreover, the synchronous clear emulation circuit is configured to emulate a synchronous clear port by using the asynchronous clear port. The synchronous clear port is emulated by outputting a data output signal that is synchronous with the clock signal and the data output signal is based on an asynchronous clear signal received at the asynchronous clear port. The asynchronous clear port performs a function of the asynchronous clear port without the synchronous clear port implemented within the register.

摘要翻译： 提供同步清除仿真电路。 同步清除仿真电路包括具有异步清除端口的寄存器。 此外，同步清除仿真电路被配置为通过使用异步清除端口来模拟同步清除端口。 通过输出与时钟信号同步的数据输出信号来仿真同步清除端口，并且数据输出信号基于在异步清除端口处接收的异步清除信号。 异步清除端口执行异步清除端口的功能，而不在寄存器内实现同步清除端口。

公开(公告)号：US08248110B1

公开(公告)日：2012-08-21

申请号：US13048241

申请日：2011-03-15

申请人： Gary Lai ,  Andy L. Lee ,  Ryan Fung ,  Vaughn Betz ,  Marcel A. LeBlanc

发明人： Gary Lai ,  Andy L. Lee ,  Ryan Fung ,  Vaughn Betz ,  Marcel A. LeBlanc

IPC分类号： H01H71/22

CPC分类号： G06F1/10

摘要： Clock switch-over circuits and methods provide clock signals to clock routing networks. According to one embodiment, a multiplexer selects between a first clock signal and a second clock signal in response to a switch select signal received from a control circuit. A storage circuit stores an enable signal in response to an output clock signal of the multiplexer. A logic circuit transmits the output clock signal of the multiplexer to a clock routing network in response to the enable signal from the storage circuit. At least one signal is transmitted from the clock switch-over circuit to the control circuit.

摘要翻译： 时钟切换电路和方法为时钟路由网络提供时钟信号。 根据一个实施例，多路复用器响应于从控制电路接收的开关选择信号在第一时钟信号和第二时钟信号之间进行选择。 存储电路响应于多路复用器的输出时钟信号而存储使能信号。 响应于来自存储电路的使能信号，逻辑电路将多路复用器的输出时钟信号传输到时钟路由网络。 至少一个信号从时钟切换电路发送到控制电路。

公开(公告)号：US07107567B1

公开(公告)日：2006-09-12

申请号：US10819783

申请日：2004-04-06

申请人： Marcel A. LeBlanc

发明人： Marcel A. LeBlanc

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5045

摘要： Protected electronic designs permit appropriate simulation and testing of the electronic design in a simulation environment, while preventing a correctly operating unauthorized implementation of the electronic design in a hardware environment such as a programmable device. An unprotected version of the simulation version of an electronic design is augmented by adding protection circuitry to the unprotected version to create a protected version of the electronic design, which operates correctly in a simulation environment but which fails to operate correctly in a hardware environment. In some embodiments of the present invention, a separate programming version which does not incorporate the protection circuitry of the simulation version may also be provided for licensed/authorized users of the electronic design, which may be an IP core or other design.

摘要翻译： 受保护的电子设计允许在模拟环境中适当地模拟和测试电子设计，同时防止在诸如可编程设备的硬件环境中正确地操作未经授权的电子设计实施。 电子设计的模拟版本的无保护版本通过向未受保护版本添加保护电路来增强电子设计的受保护版本，该电子设计在仿真环境中正确运行，但是在硬件环境中无法正确地运行。 在本发明的一些实施例中，还可以提供不包含仿真版本的保护电路的独立编程版本，用于电子设计的许可/授权用户，其可以是IP核或其它设计。

公开(公告)号：US06401230B1

公开(公告)日：2002-06-04

申请号：US09243195

申请日：1999-02-01

申请人： Razmik Ahanessians ,  Marcel A. LeBlanc

发明人： Razmik Ahanessians ,  Marcel A. LeBlanc

IPC分类号： G06F1750

CPC分类号： G06F17/5045

摘要： Software modules referred to as “plug-ins” associate with megafunctions written in any Hardware Description Language to provide rich parameterization. To the user, the plug-ins present a “wizard” interface allowing selection or setting of any number of important parameters for a particular megafunction. To the design compiler, parameterized megafunctions instantiated via a plug-in appear non-parameterized functions of a type that may be easily handled (by, for example, VHDL and Verilog compilers). Plug-ins “plug into” a compiler or an application associated with the compiler, sometimes referred to as a “plug-in manager.” The plug-in manager creates compilable files from user-defined parameter settings passed by the plug-ins.

摘要翻译： 被称为“插件”的软件模块与以任何硬件描述语言编写的宏功能相关联，以提供丰富的参数化。 对于用户来说，插件提供了一个“向导”界面，允许选择或设置特定兆功能的任意数量的重要参数。 对于设计编译器，通过插件实例化的参数化宏功能出现可以轻松处理（例如，VHDL和Verilog编译器）类型的非参数化函数。 插件“插入”编译器或与编译器关联的应用程序，有时称为“插件管理器”。 插件管理器通过插件传递的用户定义的参数设置创建可编译的文件。