公开(公告)号：US20070113171A1

公开(公告)日：2007-05-17

申请号：US11272949

申请日：2005-11-14

申请人： Jochen Behrens ,  Marcelino Dignum ,  Wayne Seltzer ,  William Zaumen ,  John Petry ,  Santiago Pericas-Geertsen ,  Biswadeep Nag

发明人： Jochen Behrens ,  Marcelino Dignum ,  Wayne Seltzer ,  William Zaumen ,  John Petry ,  Santiago Pericas-Geertsen ,  Biswadeep Nag

IPC分类号： G06F17/00

CPC分类号： G06F15/7842

摘要： A method and apparatus for accelerating processing of a structured document. A hardware XML accelerator includes one or more processors (e.g., CMT processors), one or more hardware XML parser units, one or more cryptographic units and various interfaces (e.g., to memory, a network, a communication bus). An XML document may be processed in its entirety or may be parsed in segments (e.g., as it is received). A parser unit parses a document or segment character by character, validates characters, assembles tokens from the document, extracts data, generates token headers (to describe tokens and data) and forwards the token headers and data for consumption by an application. A cryptographic unit may enforce web security, XML security or some other security scheme, by providing encryption/decryption functionality, computing digital signatures, etc. Software processing, bus utilization and latencies (e.g., memory, bus) are greatly reduced, thereby providing significantly improved XML processing and security processing throughput.

摘要翻译： 一种用于加速结构化文档处理的方法和装置。 硬件XML加速器包括一个或多个处理器（例如，CMT处理器），一个或多个硬件XML解析器单元，一个或多个密码单元和各种接口（例如，到存储器，网络，通信总线）。 XML文档可以被整体处理，或者可以被分段（例如，被接收）来解析。 解析器单元按字符逐个解析文档或段，验证字符，从文档汇编令牌，提取数据，生成令牌标题（描述令牌和数据），并转发令牌标题和数据以供应用程序消费。 加密单元可以通过提供加密/解密功能，计算数字签名等来实施Web安全性，XML安全性或某些其他安全性方案。软件处理，总线利用和延迟（例如，存储器，总线）大大降低，从而显着提供 改进的XML处理和安全处理吞吐量。

公开(公告)号：US20070113222A1

公开(公告)日：2007-05-17

申请号：US11272843

申请日：2005-11-14

申请人： Marcelino Dignum ,  Jochen Behrens ,  Wayne Seltzer ,  William Zaumen

发明人： Marcelino Dignum ,  Jochen Behrens ,  Wayne Seltzer ,  William Zaumen

IPC分类号： G06F9/45 ,  G06F17/00

CPC分类号： G06F17/2705

摘要： A hardware unit for parsing an XML document includes embedded logic or circuitry for accessing the document, decoding it to change a character set, validating individual characters of the document, extracting tokens, maintaining a symbol table and generating binary token headers to describe the document's structure and convey the document's data to an application. Tokenization, the process of identifying tokens and generating token headers, may be controlled by a finite state machine that recognizes XML delimiters in the document's markup and activates state transitions based on the current state and the recognized delimiter. The parser unit may be implemented within a hardware XML accelerator that includes a processor, a DMA engine, a cryptographic engine, memory (e.g., for storing a document, maintaining a symbol table) and various interfaces (e.g., network, memory, bus).

摘要翻译： 用于解析XML文档的硬件单元包括用于访问文档的嵌入式逻辑或电路，对其进行解码以改变字符集，验证文档的各个字符，提取令牌，维护符号表以及生成二进制标记头来描述文档的结构 并将文档的数据传送到应用程序。 令牌化，识别令牌和生成令牌头的过程可以由识别文档标记中的XML定界符的有限状态机控制，并且基于当前状态和识别的分隔符激活状态转换。 解析器单元可以在包括处理器，DMA引擎，加密引擎，存储器（例如，用于存储文档，维护符号表）和各种接口（例如，网络，存储器，总线）的硬件XML加速器内实现， 。

公开(公告)号：US20070113172A1

公开(公告)日：2007-05-17

申请号：US11273351

申请日：2005-11-14

申请人： Jochen Behrens ,  Marcelino Dignum ,  Wayne Seltzer ,  William Zaumen

发明人： Jochen Behrens ,  Marcelino Dignum ,  Wayne Seltzer ,  William Zaumen

IPC分类号： G06F17/00 ,  G06F15/00

CPC分类号： G06F17/2247 ,  G06F17/2229

摘要： A method and apparatus for performing virtualized parsing of an XML document. A document is divided into multiple segments, which may correspond to separate packets containing portions of the document, disk blocks, memory pages, etc. For each segment, a processor operating within an XML accelerator initiates parsing by identifying to a hardware parsing unit the document segment, a symbol table for the document and a location for storing state information regarding the parsing. Each segment is parsed in sequence, and the state information of the parsing is stored after each segment is completed, for retrieval when the next segment is to be parsed.

摘要翻译： 一种用于执行XML文档的虚拟解析的方法和装置。 文档被分成多个段，其可以对应于包含文档，磁盘块，存储器页面等的部分的单独的分组。对于每个段，在XML加速器中操作的处理器通过向硬件解析单元标识文档来启动解析 段，文档的符号表和用于存储关于解析的状态信息的位置。 每个段按顺序进行解析，并且在每个段完成之后存储解析的状态信息，以便在下一个段被解析时进行检索。

公开(公告)号：US20070113170A1

公开(公告)日：2007-05-17

申请号：US11272762

申请日：2005-11-14

申请人： Marcelino Dignum ,  Jochen Behrens ,  Wayne Seltzer

发明人： Marcelino Dignum ,  Jochen Behrens ,  Wayne Seltzer

IPC分类号： G06F17/00

CPC分类号： G06F17/2247 ,  G06F17/272 ,  G06F17/2775

摘要： A hardware finite state machine for facilitating the processing of an XML (Extensible Markup Language) document or other structured data stream. An accelerator is implemented in hardware to enable fast processing of a document (or a segment thereof). The accelerator includes a finite state machine that embodies a ternary CAM (Content-Addressable Memory) and associated RAM (Random Access Memory). Processing of the document is divided into multiple states, with each state transition defined by a markup delimiter that triggers the transition. The CAM is programmed with entries containing the processing states and, for each possible transition from that state, a pattern for matching delimiters that trigger the possible transitions. For a CAM entry matching the current processing state and a sequence of characters from the document, which may contain a delimiter, the associated RAM identifies the next state and any action to be taken (e.g., to shift the sequence of characters).

摘要翻译： 一种用于促进XML（可扩展标记语言）文档或其他结构化数据流的处理的硬件有限状态机。 加速器在硬件中实现，以便能够快速处理文档（或其部分）。 加速器包括体现三元CAM（内容可寻址存储器）和相关RAM（随机存取存储器）的有限状态机。 文档的处理分为多个状态，每个状态转换由触发转换的标记分隔符定义。 使用包含处理状态的条目对CAM进行编程，并且对于从该状态的每个可能的转变，用于匹配定界符的模式来触发可能的转换。 对于与当前处理状态匹配的CAM条目和来自文档的可能包含分隔符的字符序列，相关联的RAM识别下一个状态和要采取的任何动作（例如，移动字符序列）。

公开(公告)号：US07020146B2

公开(公告)日：2006-03-28

申请号：US09943566

申请日：2001-08-30

申请人： Brian L. Smith ,  Wayne Seltzer ,  Andrew Clayton

发明人： Brian L. Smith ,  Wayne Seltzer ,  Andrew Clayton

IPC分类号： H04L12/28

CPC分类号： H04L49/254 ,  H04L12/185 ,  H04L49/201 ,  H04L49/351

摘要： A method and mechanism for arbitrating and transmitting data. A first transaction and a second transaction are detected. The first transaction is targeted to a first domain and the second transaction is targeted to a second domain different than the first domain. Subsequent to receiving the transactions, arbitration domains corresponding to each are determined. In response to detecting the arbitration domains are not equal, the first and second transaction may be transmitted concurrently. However, if the arbitration domains are determined to be equal, arbitration is performed and transmission of the first and second transactions is serialized. Also contemplated is generating masks corresponding to each of the received transactions. The masks which are generated include an indication of the target domain of the corresponding transaction. When the transaction is conveyed to a port for transmittal, its mask is conveyed as well. Each port includes a domain vector register indicating the domains to which it is connected. By comparing the received mask to the domain vector register, a determination is made as to whether the transaction is to be output on the port or not.