公开(公告)号：US20100058128A1

公开(公告)日：2010-03-04

申请号：US12549747

申请日：2009-08-28

Applicant: Marco CASARSA

Inventor： Marco CASARSA

IPC: G11C29/00

CPC classification number: G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C2029/0401

Abstract: A shared diagnosis method may be for an electronic integrated system embedding a plurality of memory units associated with Built In Self Test (BIST) hardware portions for executing a test on memory locations of the memory units. A FAIL signal may be provided from the hardware portions, together with the memory locations of the memory units on which the test is executed. The method may include loading of address, state and data signals, generated during the test on the memory locations, in a series of bitmapping registers and supplied by multiplexer devices, which receive as inputs the address, state, and data signals from the memory units and from the hardware portions. The enabling for the loading of the bitmapping registers is through the processing of a Fail signal in a counter supplied by a multiplexer device receiving the Fail signals from the hardware portions.

Abstract translation: 共享诊断方法可以是嵌入与内置自检（BIST）硬件部分相关联的多个存储器单元的电子集成系统，用于对存储器单元的存储器位置执行测试。 可以从硬件部分以及执行测试的存储器单元的存储器位置提​​供FAIL信号。 该方法可以包括在测试中产生的地址，状态和数据信号在一系列位图寄存器中加载并由多路复用器设备提供，其从存储器单元接收地址，状态和数据信号作为输入 和硬件部分。 加载位图寄存器的启用是通过处理从由硬件部分接收到失败信号的多路复用器装置提供的计数器中的失败信号。

公开(公告)号：US20070300116A1

公开(公告)日：2007-12-27

申请号：US11759625

申请日：2007-06-07

Applicant: Marco CASARSA

Inventor： Marco CASARSA

IPC: G01R31/28 ,  G06F11/00

CPC classification number: H03K19/1737 ,  G01R31/318541 ,  H03K3/037

Abstract: An asynchronous set-reset circuit device for testing activity performed by an Automatic Test Patterns Generation tool may include a pair of logic gates having at least two inputs each, and a logic gate structure coupled upstream from the pair of logic gates. The logic gate structure may be for driving one respective input of the pair of logic gates and may have inputs receiving a pair of test command signals. The asynchronous set-reset circuit device may also include a plurality of feedback connections between outputs of the pair of logic gates and respective inputs of the logic gate structure.

Abstract translation: 用于测试由自动测试模式生成工具执行的活动的异步设置复位电路设备可以包括一对具有至少两个输入的逻辑门，以及耦合在该对逻辑门上游的逻辑门结构。 逻辑门结构可以用于驱动一对逻辑门的一个相应输入，并且可以具有接收一对测试命令信号的输入。 异步设置复位电路器件还可以包括在该逻辑门对的输出和逻辑门结构的相应输入之间的多个反馈连接。